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| author | Roger Sayle <roger@nextmovesoftware.com> | 2022-01-07 09:57:21 +0000 |
|---|---|---|
| committer | Roger Sayle <roger@nextmovesoftware.com> | 2022-01-07 09:57:21 +0000 |
| commit | 659f8161f61d3f75c3a47cf646147e8f7b4dcb34 (patch) | |
| tree | 0b74b1a131369f0ca8adadd4e8f835ea6b951594 /gcc/config | |
| parent | add37d3bf4f375bb202abdc7cf7768f27fc968d7 (diff) | |
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nvptx: Add support for PTX's cnot instruction.
This is a simple patch, now that the nvptx backend has transitioned
to STORE_FLAG_VALUE=1, that adds support for NVidia's cnot instruction,
that implements C/C++ style logical negation.
Previously, the simple function:
int foo(int x) { return !x; }
on nvptx-none with -O2 would generate:
mov.u32 %r24, %ar0;
setp.eq.u32 %r28, %r24, 0;
selp.u32 %value, 1, 0, %r28;
with this patch, GCC now generates:
mov.u32 %r24, %ar0;
cnot.b32 %value, %r24;
2022-01-07 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* config/nvptx/nvptx.md (*cnot<mode>2): New define_insn.
gcc/testsuite/ChangeLog
* gcc.target/nvptx/cnot-1.c: New test case.
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/nvptx/nvptx.md | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md index a4c14a3..ce74672 100644 --- a/gcc/config/nvptx/nvptx.md +++ b/gcc/config/nvptx/nvptx.md @@ -592,6 +592,13 @@ "" "%.\\tnot.b%T0\\t%0, %1;") +(define_insn "*cnot<mode>2" + [(set (match_operand:HSDIM 0 "nvptx_register_operand" "=R") + (eq:HSDIM (match_operand:HSDIM 1 "nvptx_register_operand" "R") + (const_int 0)))] + "" + "%.\\tcnot.b%T0\\t%0, %1;") + (define_insn "bitrev<mode>2" [(set (match_operand:SDIM 0 "nvptx_register_operand" "=R") (unspec:SDIM [(match_operand:SDIM 1 "nvptx_register_operand" "R")] |