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| author | Tejas Belagod <tejas.belagod@arm.com> | 2013-11-22 15:27:23 +0000 |
|---|---|---|
| committer | Tejas Belagod <belagod@gcc.gnu.org> | 2013-11-22 15:27:23 +0000 |
| commit | 635ad37e5a2406b5c7831bb820392aa173e0e433 (patch) | |
| tree | e52ebaf4ce39f8f0007448f67ec4239936ad982d /gcc/config | |
| parent | 8400e75ec451d9ecaf58ec1c07a29824a31a2e0a (diff) | |
| download | gcc-635ad37e5a2406b5c7831bb820392aa173e0e433.zip gcc-635ad37e5a2406b5c7831bb820392aa173e0e433.tar.gz gcc-635ad37e5a2406b5c7831bb820392aa173e0e433.tar.bz2 | |
aarch64-simd.md (*aarch64_simd_mov<mode>): Fix loads and stores to be ABI compliant.
2013-11-22 Tejas Belagod <tejas.belagod@arm.com>
gcc/
* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): Fix loads
and stores to be ABI compliant.
From-SVN: r205266
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index b9ebdf5..19ef203 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -85,17 +85,17 @@ (define_insn "*aarch64_simd_mov<mode>" [(set (match_operand:VD 0 "aarch64_simd_nonimmediate_operand" - "=w, Utv, w, ?r, ?w, ?r, w") + "=w, m, w, ?r, ?w, ?r, w") (match_operand:VD 1 "aarch64_simd_general_operand" - "Utv, w, w, w, r, r, Dn"))] + "m, w, w, w, r, r, Dn"))] "TARGET_SIMD && (register_operand (operands[0], <MODE>mode) || register_operand (operands[1], <MODE>mode))" { switch (which_alternative) { - case 0: return "ld1\t{%0.<Vtype>}, %1"; - case 1: return "st1\t{%1.<Vtype>}, %0"; + case 0: return "ldr\\t%d0, %1"; + case 1: return "str\\t%d1, %0"; case 2: return "orr\t%0.<Vbtype>, %1.<Vbtype>, %1.<Vbtype>"; case 3: return "umov\t%0, %1.d[0]"; case 4: return "ins\t%0.d[0], %1"; @@ -113,9 +113,9 @@ (define_insn "*aarch64_simd_mov<mode>" [(set (match_operand:VQ 0 "aarch64_simd_nonimmediate_operand" - "=w, Utv, w, ?r, ?w, ?r, w") + "=w, m, w, ?r, ?w, ?r, w") (match_operand:VQ 1 "aarch64_simd_general_operand" - "Utv, w, w, w, r, r, Dn"))] + "m, w, w, w, r, r, Dn"))] "TARGET_SIMD && (register_operand (operands[0], <MODE>mode) || register_operand (operands[1], <MODE>mode))" @@ -123,9 +123,9 @@ switch (which_alternative) { case 0: - return "ld1\t{%0.<Vtype>}, %1"; + return "ldr\\t%q0, %1"; case 1: - return "st1\t{%1.<Vtype>}, %0"; + return "str\\t%q1, %0"; case 2: return "orr\t%0.<Vbtype>, %1.<Vbtype>, %1.<Vbtype>"; case 3: |