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| author | Andrew Stubbs <ams@codesourcery.com> | 2021-11-25 15:59:20 +0000 |
|---|---|---|
| committer | Andrew Stubbs <ams@codesourcery.com> | 2021-11-25 16:04:00 +0000 |
| commit | 58d50a5dd6344179eebaeb6fd2f895e59463cf74 (patch) | |
| tree | 2f99d49e84ad3e2cba2debf6da883f375d505095 /gcc/config | |
| parent | 1598bd47b2a4a5f12b5a987d16d82634644db4b6 (diff) | |
| download | gcc-58d50a5dd6344179eebaeb6fd2f895e59463cf74.zip gcc-58d50a5dd6344179eebaeb6fd2f895e59463cf74.tar.gz gcc-58d50a5dd6344179eebaeb6fd2f895e59463cf74.tar.bz2 | |
amdgcn: Fix ICE generating CFI [PR103396]
gcc/ChangeLog:
PR target/103396
* config/gcn/gcn.c (move_callee_saved_registers): Ensure that the
number of spilled registers is counted correctly.
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/gcn/gcn.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c index 75a9c57..2bde88a 100644 --- a/gcc/config/gcn/gcn.c +++ b/gcc/config/gcn/gcn.c @@ -2785,7 +2785,7 @@ move_callee_saved_registers (rtx sp, machine_function *offsets, int start = (regno == VGPR_REGNO (7) ? 64 : 0); int count = MIN (saved_scalars - start, 64); int add_lr = (regno == VGPR_REGNO (6) - && df_regs_ever_live_p (LINK_REGNUM)); + && offsets->lr_needs_saving); int lrdest = -1; rtvec seq = rtvec_alloc (count + add_lr); |