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author | Michael Meissner <michael.meissner@amd.com> | 2008-05-14 18:02:56 +0000 |
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committer | Michael Meissner <meissner@gcc.gnu.org> | 2008-05-14 18:02:56 +0000 |
commit | 550c9cf0fe26d6da75cfaeea41a766fe69ddee4e (patch) | |
tree | e586103b9b131850957e0684036b2ce01a0cb802 /gcc/config | |
parent | 61ab1651b91da9c63f78ea93b89117867188979d (diff) | |
download | gcc-550c9cf0fe26d6da75cfaeea41a766fe69ddee4e.zip gcc-550c9cf0fe26d6da75cfaeea41a766fe69ddee4e.tar.gz gcc-550c9cf0fe26d6da75cfaeea41a766fe69ddee4e.tar.bz2 |
Fix pr36224
From-SVN: r135302
Diffstat (limited to 'gcc/config')
-rw-r--r-- | gcc/config/i386/sse.md | 38 |
1 files changed, 0 insertions, 38 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 983ffcf..88822c5 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -3357,44 +3357,6 @@ DONE; }) -(define_expand "vec_widen_smult_hi_v4si" - [(match_operand:V2DI 0 "register_operand" "") - (match_operand:V4SI 1 "register_operand" "") - (match_operand:V4SI 2 "register_operand" "")] - "TARGET_SSE2" -{ - rtx op1, op2, t1, t2; - - op1 = operands[1]; - op2 = operands[2]; - t1 = gen_reg_rtx (V4SImode); - t2 = gen_reg_rtx (V4SImode); - - emit_insn (gen_vec_interleave_highv4si (t1, op1, op1)); - emit_insn (gen_vec_interleave_highv4si (t2, op2, op2)); - emit_insn (gen_sse2_umulv2siv2di3 (operands[0], t1, t2)); - DONE; -}) - -(define_expand "vec_widen_smult_lo_v4si" - [(match_operand:V2DI 0 "register_operand" "") - (match_operand:V4SI 1 "register_operand" "") - (match_operand:V4SI 2 "register_operand" "")] - "TARGET_SSE2" -{ - rtx op1, op2, t1, t2; - - op1 = operands[1]; - op2 = operands[2]; - t1 = gen_reg_rtx (V4SImode); - t2 = gen_reg_rtx (V4SImode); - - emit_insn (gen_vec_interleave_lowv4si (t1, op1, op1)); - emit_insn (gen_vec_interleave_lowv4si (t2, op2, op2)); - emit_insn (gen_sse2_umulv2siv2di3 (operands[0], t1, t2)); - DONE; -}) - (define_expand "vec_widen_umult_hi_v4si" [(match_operand:V2DI 0 "register_operand" "") (match_operand:V4SI 1 "register_operand" "") |