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| author | Richard Sandiford <rsandifo@nildram.co.uk> | 2007-09-23 19:20:01 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2007-09-23 19:20:01 +0000 |
| commit | 50b73fcde42694209997f01f9985dc5928a86fca (patch) | |
| tree | a8648e832edade747b376a4adc7c7e6d63a494aa /gcc/config | |
| parent | e9276c30128632a6578dcf011caddedda6acf48e (diff) | |
| download | gcc-50b73fcde42694209997f01f9985dc5928a86fca.zip gcc-50b73fcde42694209997f01f9985dc5928a86fca.tar.gz gcc-50b73fcde42694209997f01f9985dc5928a86fca.tar.bz2 | |
mips.c (build_mips16_call_stub): On 64-bit targets, combine an SC return value into a single register.
gcc/
* config/mips/mips.c (build_mips16_call_stub): On 64-bit targets,
combine an SC return value into a single register.
From-SVN: r128700
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/mips/mips.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index e6b17a5..39d5e37 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -10055,6 +10055,19 @@ build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code) fprintf (asm_out_file, "\tmfc1\t%s,%s\n", reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]); + if (GET_MODE (retval) == SCmode && TARGET_64BIT) + { + /* On 64-bit targets, complex floats are returned in + a single GPR, such that "sd" on a suitably-aligned + target would store the value correctly. */ + fprintf (asm_out_file, "\tdsll\t%s,%s,32\n", + reg_names[GP_REG_FIRST + 2 + TARGET_LITTLE_ENDIAN], + reg_names[GP_REG_FIRST + 2 + TARGET_LITTLE_ENDIAN]); + fprintf (asm_out_file, "\tor\t%s,%s,%s\n", + reg_names[GP_REG_FIRST + 2], + reg_names[GP_REG_FIRST + 2], + reg_names[GP_REG_FIRST + 3]); + } break; case DCmode: |