diff options
| author | Fariborz Jahanian <fjahanian@apple.com> | 2005-06-10 15:01:59 +0000 |
|---|---|---|
| committer | Fariborz Jahanian <fjahanian@gcc.gnu.org> | 2005-06-10 15:01:59 +0000 |
| commit | 4a96e5c3cd07bf5b4860fdb55510682f9d708e71 (patch) | |
| tree | e40684a215a637b820559186d0071f3dfe3e5a20 /gcc/config | |
| parent | bb7483290049647685d17557117e4285530266f3 (diff) | |
| download | gcc-4a96e5c3cd07bf5b4860fdb55510682f9d708e71.zip gcc-4a96e5c3cd07bf5b4860fdb55510682f9d708e71.tar.gz gcc-4a96e5c3cd07bf5b4860fdb55510682f9d708e71.tar.bz2 | |
Use scc_operand predicate for eq:SI in powerpc.
Oked by David Edelsohn.
From-SVN: r100818
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/rs6000/predicates.md | 11 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 12 |
2 files changed, 17 insertions, 6 deletions
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index a2daf87..936f932 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -132,6 +132,17 @@ (ior (match_code "const_int") (match_operand 0 "gpc_reg_operand"))) +;; Return 1 if op is an integer meeting one of 'I','J','O','L'(TARGET_32BIT) +;; or 'J'(TARGET_64BIT) constraints or if it is a non-special register. +(define_predicate "scc_operand" + (if_then_else (match_code "const_int") + (match_test "CONST_OK_FOR_LETTER_P (INTVAL (op), 'I') + || CONST_OK_FOR_LETTER_P (INTVAL (op), 'K') + || CONST_OK_FOR_LETTER_P (INTVAL (op), 'O') + || CONST_OK_FOR_LETTER_P (INTVAL (op), + (TARGET_32BIT ? 'L' : 'J'))") + (match_operand 0 "gpc_reg_operand"))) + ;; Return 1 if op is a 32-bit signed constant integer valid for arithmetic ;; or non-special register. (define_predicate "reg_or_arith_cint_operand" diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 2f3331b..ead5f03 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -11560,7 +11560,7 @@ (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r") (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) + (match_operand:SI 2 "scc_operand" "r,O,K,L,I")) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] "TARGET_32BIT" "@ @@ -11577,7 +11577,7 @@ (compare:CC (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) + (match_operand:SI 2 "scc_operand" "r,O,K,L,I,r,O,K,L,I")) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] @@ -11601,7 +11601,7 @@ (compare:CC (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) + (match_operand:SI 2 "scc_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:SI 4 ""))] @@ -11620,7 +11620,7 @@ (compare:CC (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) + (match_operand:SI 2 "scc_operand" "r,O,K,L,I,r,O,K,L,I")) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r") @@ -11645,7 +11645,7 @@ (compare:CC (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) + (match_operand:SI 2 "scc_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") @@ -11661,7 +11661,7 @@ (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] + (match_operand:SI 2 "scc_operand" "r,O,K,L,I"))))] "TARGET_32BIT" "@ xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |