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author | Jason Merrill <jason@redhat.com> | 2001-02-08 21:00:44 -0500 |
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committer | Jason Merrill <jason@gcc.gnu.org> | 2001-02-08 21:00:44 -0500 |
commit | 34ce3d7ba5a482d79a56dcbdfe72c7fbf5932c63 (patch) | |
tree | 3c4a4455cb22bad2dd8d24ed45b3202db90aee51 /gcc/config | |
parent | 8a5f950e04d5f96083ffe0898c072efc51435c28 (diff) | |
download | gcc-34ce3d7ba5a482d79a56dcbdfe72c7fbf5932c63.zip gcc-34ce3d7ba5a482d79a56dcbdfe72c7fbf5932c63.tar.gz gcc-34ce3d7ba5a482d79a56dcbdfe72c7fbf5932c63.tar.bz2 |
arm.c (arm_expand_prologue): Do tell the dwarf2 backend about the SP adjustment for saving the static chain...
* config/arm/arm.c (arm_expand_prologue): Do tell the dwarf2 backend
about the SP adjustment for saving the static chain pointer.
* dwarf2out.c (dwarf2out_frame_debug_expr): Use the specified
offset when setting a temporary CFA register.
From-SVN: r39554
Diffstat (limited to 'gcc/config')
-rw-r--r-- | gcc/config/arm/arm.c | 23 |
1 files changed, 14 insertions, 9 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 53dd0dd..d906b14 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -7804,27 +7804,34 @@ arm_expand_prologue () If neither of these places is available, we abort (for now). - Note - setting RTX_FRAME_RELATED_P on these insns breaks - the dwarf2 parsing code in various bits of gcc. This ought - to be fixed sometime, but until then the flag is suppressed. - [Use gcc/testsuite/gcc.c-torture/execute/921215-1.c with - "-O3 -g" to test this]. */ + Note - we only need to tell the dwarf2 backend about the SP + adjustment in the second variant; the static chain register + doesn't need to be unwound, as it doesn't contain a value + inherited from the caller. */ if (regs_ever_live[3] == 0) { insn = gen_rtx_REG (SImode, 3); insn = gen_rtx_SET (SImode, insn, ip_rtx); insn = emit_insn (insn); - /* RTX_FRAME_RELATED_P (insn) = 1; */ } else if (current_function_pretend_args_size == 0) { + rtx dwarf; insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx); insn = gen_rtx_MEM (SImode, insn); insn = gen_rtx_SET (VOIDmode, insn, ip_rtx); insn = emit_insn (insn); - /* RTX_FRAME_RELATED_P (insn) = 1; */ + fp_offset = 4; + + /* Just tell the dwarf backend that we adjusted SP. */ + dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, + gen_rtx_PLUS (SImode, stack_pointer_rtx, + GEN_INT (-fp_offset))); + RTX_FRAME_RELATED_P (insn) = 1; + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, + dwarf, REG_NOTES (insn)); } else /* FIXME - the way to handle this situation is to allow @@ -7931,7 +7938,6 @@ arm_expand_prologue () insn = gen_rtx_REG (SImode, 3); insn = gen_rtx_SET (SImode, ip_rtx, insn); insn = emit_insn (insn); - /* RTX_FRAME_RELATED_P (insn) = 1; */ } else /* if (current_function_pretend_args_size == 0) */ { @@ -7939,7 +7945,6 @@ arm_expand_prologue () insn = gen_rtx_MEM (SImode, insn); insn = gen_rtx_SET (SImode, ip_rtx, insn); insn = emit_insn (insn); - /* RTX_FRAME_RELATED_P (insn) = 1; */ } } } |