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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2015-12-16 15:03:44 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2015-12-16 15:03:44 +0000 |
| commit | 3297949ea9b4b350f0ccc97f289d9d918c9ba8c7 (patch) | |
| tree | 3466fe18e2dca6219b230ff32adceb3adac9bfd3 /gcc/config | |
| parent | 7b5ab0cdc1e9deb628f98ced5f6e80703a8835f3 (diff) | |
| download | gcc-3297949ea9b4b350f0ccc97f289d9d918c9ba8c7.zip gcc-3297949ea9b4b350f0ccc97f289d9d918c9ba8c7.tar.gz gcc-3297949ea9b4b350f0ccc97f289d9d918c9ba8c7.tar.bz2 | |
[AArch64] PR target/68696 FAIL: gcc.target/aarch64/vbslq_u64_1.c scan-assembler-times bif\tv 1
PR target/68696
* config/aarch64/aarch64-simd.md (*aarch64_simd_bsl<mode>_alt):
New pattern.
(aarch64_simd_bsl<mode>_internal): Update comment to reflect
the above.
From-SVN: r231696
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 030a101..2856f01 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -2153,6 +2153,10 @@ ;; bit op0, op2, mask ;; if (op0 = op2) (so 0-bits in mask choose bits from op1, else op0) ;; bif op0, op1, mask +;; +;; This pattern is expanded to by the aarch64_simd_bsl<mode> expander. +;; Some forms of straight-line code may generate the equivalent form +;; in *aarch64_simd_bsl<mode>_alt. (define_insn "aarch64_simd_bsl<mode>_internal" [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=w,w,w") @@ -2172,6 +2176,29 @@ [(set_attr "type" "neon_bsl<q>")] ) +;; We need this form in addition to the above pattern to match the case +;; when combine tries merging three insns such that the second operand of +;; the outer XOR matches the second operand of the inner XOR rather than +;; the first. The two are equivalent but since recog doesn't try all +;; permutations of commutative operations, we have to have a separate pattern. + +(define_insn "*aarch64_simd_bsl<mode>_alt" + [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=w,w,w") + (xor:VSDQ_I_DI + (and:VSDQ_I_DI + (xor:VSDQ_I_DI + (match_operand:VSDQ_I_DI 3 "register_operand" "w,w,0") + (match_operand:VSDQ_I_DI 2 "register_operand" "w,0,w")) + (match_operand:VSDQ_I_DI 1 "register_operand" "0,w,w")) + (match_dup:VSDQ_I_DI 2)))] + "TARGET_SIMD" + "@ + bsl\\t%0.<Vbtype>, %3.<Vbtype>, %2.<Vbtype> + bit\\t%0.<Vbtype>, %3.<Vbtype>, %1.<Vbtype> + bif\\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>" + [(set_attr "type" "neon_bsl<q>")] +) + (define_expand "aarch64_simd_bsl<mode>" [(match_operand:VALLDIF 0 "register_operand") (match_operand:<V_cmp_result> 1 "register_operand") |