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| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2016-01-06 19:19:47 +0000 |
|---|---|---|
| committer | William Schmidt <wschmidt@gcc.gnu.org> | 2016-01-06 19:19:47 +0000 |
| commit | 329289313c67f0ce8db19746e5c6d2601e853b3b (patch) | |
| tree | c8b465838383af87b6f65a286865bdd14db401bd /gcc/config | |
| parent | e9b596c13252df2f1cea3f27183e9969ede54fbd (diff) | |
| download | gcc-329289313c67f0ce8db19746e5c6d2601e853b3b.zip gcc-329289313c67f0ce8db19746e5c6d2601e853b3b.tar.gz gcc-329289313c67f0ce8db19746e5c6d2601e853b3b.tar.bz2 | |
vsx.md (*p9_vecload_<mode>): Replace VSX_M mode iterator with VSX_M2.
[gcc]
2015-01-06 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/vsx.md (*p9_vecload_<mode>): Replace VSX_M
mode iterator with VSX_M2.
(*p9_vecstore_<mode>): Likewise.
(*vsx_le_permute_<mode>): Restrict to !TARGET_P9_VECTOR.
(*vsx_le_perm_load_<mode> for VSX_LE_128): Likewise.
(*vsx_le_perm_store_<mode> for VSX_LE_128): Likewise.
(define_split for VSX_LE128 stores): Likewise.
(define_peephole2 for TImode LE swaps): Likewise.
(define_split for VSX_LE128 post-reload stores): Likewise.
[gcc/testsuite]
2015-01-06 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* gcc.target/powerpc/p9-lxvx-stxvx-3.c: New test.
From-SVN: r232109
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 4606bff2..997ff31 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -304,16 +304,16 @@ ;; VSX (P9) moves (define_insn "*p9_vecload_<mode>" - [(set (match_operand:VSX_M 0 "vsx_register_operand" "=<VSa>") - (match_operand:VSX_M 1 "memory_operand" "Z"))] + [(set (match_operand:VSX_M2 0 "vsx_register_operand" "=<VSa>") + (match_operand:VSX_M2 1 "memory_operand" "Z"))] "TARGET_P9_VECTOR" "lxvx %x0,%y1" [(set_attr "type" "vecload") (set_attr "length" "4")]) (define_insn "*p9_vecstore_<mode>" - [(set (match_operand:VSX_M 0 "memory_operand" "=Z") - (match_operand:VSX_M 1 "vsx_register_operand" "<VSa>"))] + [(set (match_operand:VSX_M2 0 "memory_operand" "=Z") + (match_operand:VSX_M2 1 "vsx_register_operand" "<VSa>"))] "TARGET_P9_VECTOR" "stxvx %x1,%y0" [(set_attr "type" "vecstore") @@ -680,7 +680,7 @@ (rotate:VSX_LE_128 (match_operand:VSX_LE_128 1 "input_operand" "<VSa>,Z,<VSa>") (const_int 64)))] - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "@ xxpermdi %x0,%x1,%x1,2 lxvd2x %x0,%y1 @@ -714,9 +714,9 @@ (define_insn_and_split "*vsx_le_perm_load_<mode>" [(set (match_operand:VSX_LE_128 0 "vsx_register_operand" "=<VSa>") (match_operand:VSX_LE_128 1 "memory_operand" "Z"))] - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" [(set (match_dup 2) (rotate:VSX_LE_128 (match_dup 1) (const_int 64))) @@ -735,7 +735,7 @@ (define_insn "*vsx_le_perm_store_<mode>" [(set (match_operand:VSX_LE_128 0 "memory_operand" "=Z") (match_operand:VSX_LE_128 1 "vsx_register_operand" "+<VSa>"))] - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" [(set_attr "type" "vecstore") (set_attr "length" "12")]) @@ -743,7 +743,7 @@ (define_split [(set (match_operand:VSX_LE_128 0 "memory_operand" "") (match_operand:VSX_LE_128 1 "vsx_register_operand" ""))] - "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed && !TARGET_P9_VECTOR" [(set (match_dup 2) (rotate:VSX_LE_128 (match_dup 1) (const_int 64))) @@ -765,7 +765,7 @@ (set (match_operand:TI 2 "vsx_register_operand" "") (rotate:TI (match_dup 0) (const_int 64)))] - "!BYTES_BIG_ENDIAN && TARGET_VSX && TARGET_VSX_TIMODE + "!BYTES_BIG_ENDIAN && TARGET_VSX && TARGET_VSX_TIMODE && !TARGET_P9_VECTOR && (rtx_equal_p (operands[0], operands[2]) || peep2_reg_dead_p (2, operands[0]))" [(set (match_dup 2) (match_dup 1))]) @@ -775,7 +775,7 @@ (define_split [(set (match_operand:VSX_LE_128 0 "memory_operand" "") (match_operand:VSX_LE_128 1 "vsx_register_operand" ""))] - "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed" + "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed && !TARGET_P9_VECTOR" [(set (match_dup 1) (rotate:VSX_LE_128 (match_dup 1) (const_int 64))) |