mips.h (ISA_HAS_DSP, [...]): New macros.

gcc/
	* config/mips/mips.h (ISA_HAS_DSP, ISA_HAS_DSPR2): New macros.
	* config/mips/mips.c (mips_set_mips16_mode): Don't clear the DSP
	flags for MIPS16.
	(override_options): Check TARGET_HARD_FLOAT_ABI instead of
	TARGET_HARD_FLOAT when testing whether -mpaired-single is
	supported.
	(mips_conditional_register_usage): Check ISA_HAS_DSP instead of
	TARGET_DSP.
	* config/mips/constraints.md (ka): Check ISA_HAS_DSPR2 instead of
	TARGET_DSPR2.
	* config/mips/mips.md (ANYF): Require TARGET_HARD_FLOAT for V2SF.
	(mulv2sf3, movv2sf, movv2sf_hardfloat_64bit): Require
	TARGET_HARD_FLOAT.
	(<u>mulsidi3_32bit_internal, <u>msubsidi4, <u>maddsidi4): Check
	ISA_HAS_DSPR2 instead of TARGET_HAS_DSPR2.
	* config/mips/mips-dsp.md: Use ISA_HAS_DSP instead of TARGET_HAS_DSP
	throughout.
	* config/mips/mips-dspr2.md: Likewise ISA_HAS_DSPR2 and
	TARGET_HAS_DSPR2.
	* config/mips/mips-fixed.md: Use ISA_HAS_DSP and ISA_HAS_DSPR2
	instead of TARGET_HAS_DSP and TARGET_HAS_DSPR2.
	* config/mips/mips-ps-3d.md: Add TARGET_HARD_FLOAT to V2SF patterns.

gcc/testsuite/
	* lib/target-supports.exp (check_effective_target_nomips16): New
	procedure.
	* lib/fortran-torture.exp: Check nomips16 as well as mpaired_single
	for mipsisa64*-*-*.
	* gcc.dg/vect/vect.exp: Likewise.
	* g++.dg/vect/vect.exp: Likewise.
	* gcc.target/mips/mips.exp (setup_mips_tests): Don't set mips_mips16.
	(dg-mips-options): Don't skip -march* and -mips* tests for -mips16.
	* gcc.target/mips/branch-cost-1.c (foo): Add NOMIPS16.
	* gcc.target/mips/branch-cost-2.c (foo): Likewise.
	* gcc.target/mips/clear-cache-1.c (f): Likewise.
	* gcc.target/mips/dpaq_sa_l_w.c (f1, f2, f3): Likewise.
	* gcc.target/mips/dpsq_sa_l_w.c (f1, f2, f3): Likewise.
	* gcc.target/mips/fix-vr4130-1.c (foo): Likewise.
	* gcc.target/mips/fix-vr4130-2.c (foo): Likewise.
	* gcc.target/mips/fix-vr4130-3.c (foo): Likewise.
	* gcc.target/mips/fix-vr4130-4.c (foo): Likewise.
	* gcc.target/mips/fixed-scalar-type.c (test1, test2, test3, test4)
	(test5, test6, test7, test8, test9, test10, test11, test12, test13)
	(test14, test15, test16, test17, test18): Likewise.
	* gcc.target/mips/fixed-vector-type.c (test1, test2, test3, test4)
	(test5, test6, test7, test8, test9, test10, test11, test12, test13)
	(test14, test15, test16, test17, test18, test19, test20, test21)
	(test22): Likewise.
	* gcc.target/mips/madd-1.c (f1, f2, f3): Likewise.
	* gcc.target/mips/madd-2.c (f1, f2, f3): Likewise.
	* gcc.target/mips/madd-4.c (f1, f2, f3): Likewise.
	* gcc.target/mips/maddu-1.c (f1, f2, f3): Likewise.
	* gcc.target/mips/maddu-2.c (f1, f2, f3): Likewise.
	* gcc.target/mips/maddu-4.c (f1, f2, f3): Likewise.
	* gcc.target/mips/mips-3d-1.c (main): Likewise.
	* gcc.target/mips/mips-3d-2.c (main, test0, test1, test2, test3)
	(test4, test5, test6, test7, test8, test9, test10, test11, test12)
	(test13, test14, test15, test16, test17, test18, test19, test20)
	(test21, test22, test23, test24, test25, test26, test27, test28)
	(test29, test30, test31): Likewise.
	* gcc.target/mips/mips-3d-3.c (main, test0, test1, test2, test3)
	(test4, test5, test6, test7, test8, test9, test10, test11, test12)
	(test13, test14, test15, test16, test17, test18, test19, test20)
	(test21, test22, test23, test24, test25, test26, test27, test28)
	(test29, test30, test31, test32, test33, test34, test35, test36)
	(test37, test38, test39, test40, test41, test42, test43, test44)
	(test45, test46, test47, test48, test49, test50, test51, test52)
	(test53, test54, test55, test56, test57, test58, test59, test60)
	(test61, test62, test63): Likewise.
	* gcc.target/mips/mips-3d-4.c (main, test0, test1, test2, test3)
	(test4, test5, test6, test7, test8, test9, test10, test11, test12)
	(test13, test14, test15, test16, test17, test18, test19, test20)
	(test21, test22, test23, test24, test25, test26, test27, test28)
	(test29, test30, test31): Likewise.
	* gcc.target/mips/mips-3d-5.c (main, test0, test1, test2, test3)
	(test4, test5, test6, test7, test8, test9, test10, test11, test12)
	(test13, test14, test15, test16, test17, test18, test19, test20)
	(test21, test22, test23, test24, test25, test26, test27, test28)
	(test29, test30, test31): Likewise.
	* gcc.target/mips/mips-3d-6.c (main, test0, test1, test2, test3)
	(test4, test5, test6, test7, test8, test9, test10, test11, test12)
	(test13, test14, test15): Likewise.
	* gcc.target/mips/mips-3d-7.c (main, test0, test1, test2, test3)
	(test4, test5, test6, test7, test8, test9, test10, test11, test12)
	(test13, test14, test15): Likewise.
	* gcc.target/mips/mips-3d-8.c (main, test0, test1, test2, test3)
	(test4, test5, test6, test7, test8, test9, test10, test11, test12)
	(test13, test14, test15, test16, test17, test18, test19, test20)
	(test21, test22, test23, test24, test25, test26, test27, test28)
	(test29, test30, test31): Likewise.
	* gcc.target/mips/mips-3d-9.c (matrix_multiply2, matrix_multiply3)
	(matrix_multiply4: Likewise.
	* gcc.target/mips/mips-ps-1.c (main): Likewise.
	* gcc.target/mips/mips-ps-2.c (main): Likewise.
	* gcc.target/mips/mips-ps-3.c (main): Likewise.
	* gcc.target/mips/mips-ps-4.c (main, test0, test1, test2, test3)
	(test4, test5, test6, test7, test8, test9, test10, test11, test12)
	(test13, test14, test15, test16, test17, test18, test19, test20)
	(test21, test22, test23, test24, test25, test26, test27, test28)
	(test29, test30, test31): Likewise.
	* gcc.target/mips/mips-ps-5.c (main, test0, test1, test2, test3)
	(test4, test5, test6, test7, test8, test9, test10, test11, test12)
	(test13, test14, test15, test16, test17, test18, test19, test20)
	(test21, test22, test23, test24, test25, test26, test27, test28)
	(test29, test30, test31): Likewise.
	* gcc.target/mips/mips-ps-5.c (main): Likewise.
	* gcc.target/mips/mips-ps-6.c (main): Likewise.
	* gcc.target/mips/mips-ps-type.c (init, move, load, store, add, sub)
	(neg, mul, madd, msub, nmadd, nmsub, cond_move1, cond_move2): Likewise.
	* gcc.target/mips/mips32-dsp-type.c (add_v2hi,add_v4qi, sub_v2hi)
	(sub_v4qi): Likewise.
	* gcc.target/mips/mips32-dsp.c (test_MIPS_DSP, add_v2q15, add_v4i8)
	(sub_v2q15, sub_v4i8, test_MIPS_DSP): Likewise.
	* gcc.target/mips/movcc-1.c (sub1, sub2): Likewise.
	* gcc.target/mips/movcc-2.c (sub4, sub5): Likewise.
	* gcc.target/mips/movcc-3.c (sub3, sub6, sub7, sub8, sub9, suba)
	(subb, subc): Likewise.
	* gcc.target/mips/msub-1.c (f1, f2): Likewise.
	* gcc.target/mips/msub-2.c (f1, f2): Likewise.
	* gcc.target/mips/msub-4.c (f1, f2): Likewise.
	* gcc.target/mips/msubu-1.c (f1, f2): Likewise.
	* gcc.target/mips/msubu-2.c (f1, f2): Likewise.
	* gcc.target/mips/msubu-4.c (f1, f2): Likewise.
	* gcc.target/mips/nmadd-1.c (sub1, sub2, sub3, sub4): Likewise.
	* gcc.target/mips/nmadd-2.c (sub1, sub2, sub3, sub4): Likewise.
	* gcc.target/mips/rsqrt-1.c (foo, bar): Likewise.
	* gcc.target/mips/rsqrt-2.c (foo, bar): Likewise.
	* gcc.target/mips/sb1-1.c (divide, recip, squareroot, rsqrt): Likewise.
	* gcc.target/mips/vr-mult-1.c (f1, f2): Likewise.
	* gcc.target/mips/vr-mult-2.c (f1, f2): Likewise.

From-SVN: r128683

8 files changed, 192 insertions, 189 deletions

diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md
index 98e8d6f..53e0189 100644
--- a/gcc/config/mips/constraints.md
+++ b/gcc/config/mips/constraints.md
@@ -80,7 +80,7 @@
 ;; Registers that can be used as the target of multiply-accumulate
 ;; instructions.  The core MIPS32 ISA provides a hi/lo madd,
 ;; but the DSPr2 version allows any accumulator target.
-(define_register_constraint "ka" "TARGET_DSPR2 ? ACC_REGS : MD_REGS")
+(define_register_constraint "ka" "ISA_HAS_DSPR2 ? ACC_REGS : MD_REGS")
 
 (define_constraint "kf"
   "@internal"
diff --git a/gcc/config/mips/mips-dsp.md b/gcc/config/mips/mips-dsp.md
index 60b3a94..5e6091a 100644
--- a/gcc/config/mips/mips-dsp.md
+++ b/gcc/config/mips/mips-dsp.md
@@ -7,17 +7,17 @@
    (CCDSP_EF_REGNUM	187)])
 
 ;; This mode iterator allows si, v2hi, v4qi for all possible modes in DSP ASE.
-(define_mode_iterator DSP [(SI "TARGET_DSP")
-			   (V2HI "TARGET_DSP")
-		 	   (V4QI "TARGET_DSP")])
+(define_mode_iterator DSP [(SI "ISA_HAS_DSP")
+			   (V2HI "ISA_HAS_DSP")
+		 	   (V4QI "ISA_HAS_DSP")])
 
 ;; This mode iterator allows v2hi, v4qi for vector/SIMD data.
-(define_mode_iterator DSPV [(V2HI "TARGET_DSP")
-			    (V4QI "TARGET_DSP")])
+(define_mode_iterator DSPV [(V2HI "ISA_HAS_DSP")
+			    (V4QI "ISA_HAS_DSP")])
 
 ;; This mode iterator allows si, v2hi for Q31 and V2Q15 fixed-point data.
-(define_mode_iterator DSPQ [(SI "TARGET_DSP")
-			    (V2HI "TARGET_DSP")])
+(define_mode_iterator DSPQ [(SI "ISA_HAS_DSP")
+			    (V2HI "ISA_HAS_DSP")])
 
 ;; DSP instructions use q for fixed-point data, and u for integer in the infix.
 (define_mode_attr dspfmt1 [(SI "q") (V2HI "q") (V4QI "u")])
@@ -68,7 +68,7 @@
 		      (match_operand:DSPV 2 "register_operand" "d")))
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))])]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "sub<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -81,7 +81,7 @@
 		      UNSPEC_SUBQ_S))
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "sub<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -95,7 +95,7 @@
 		     UNSPEC_ADDSC))
      (set (reg:CCDSP CCDSP_CA_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))])]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "addsc\t%0,%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -110,7 +110,7 @@
 		     UNSPEC_ADDWC))
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))])]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "addwc\t%0,%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -121,7 +121,7 @@
 	(unspec:SI [(match_operand:SI 1 "register_operand" "d")
 		    (match_operand:SI 2 "register_operand" "d")]
 		   UNSPEC_MODSUB))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "modsub\t%0,%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -131,7 +131,7 @@
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")]
 		   UNSPEC_RADDU_W_QB))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "raddu.w.qb\t%0,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -144,7 +144,7 @@
 		       UNSPEC_ABSQ_S))
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))])]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "absq_s.<DSPQ:dspfmt2>\t%0,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -155,7 +155,7 @@
 	(unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d")
 		      (match_operand:V2HI 2 "register_operand" "d")]
 		     UNSPEC_PRECRQ_QB_PH))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "precrq.qb.ph\t%0,%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -165,7 +165,7 @@
 	(unspec:V2HI [(match_operand:SI 1 "register_operand" "d")
 		      (match_operand:SI 2 "register_operand" "d")]
 		     UNSPEC_PRECRQ_PH_W))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "precrq.ph.w\t%0,%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -179,7 +179,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)]
 			UNSPEC_PRECRQ_RS_PH_W))])]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "precrq_rs.ph.w\t%0,%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -194,7 +194,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)]
 			UNSPEC_PRECRQU_S_QB_PH))])]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "precrqu_s.qb.ph\t%0,%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -204,7 +204,7 @@
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(unspec:SI [(match_operand:V2HI 1 "register_operand" "d")]
 		   UNSPEC_PRECEQ_W_PHL))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "preceq.w.phl\t%0,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -213,7 +213,7 @@
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(unspec:SI [(match_operand:V2HI 1 "register_operand" "d")]
 		   UNSPEC_PRECEQ_W_PHR))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "preceq.w.phr\t%0,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -223,7 +223,7 @@
   [(set (match_operand:V2HI 0 "register_operand" "=d")
 	(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 		     UNSPEC_PRECEQU_PH_QBL))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "precequ.ph.qbl\t%0,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -232,7 +232,7 @@
   [(set (match_operand:V2HI 0 "register_operand" "=d")
 	(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 		     UNSPEC_PRECEQU_PH_QBR))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "precequ.ph.qbr\t%0,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -241,7 +241,7 @@
   [(set (match_operand:V2HI 0 "register_operand" "=d")
 	(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 		     UNSPEC_PRECEQU_PH_QBLA))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "precequ.ph.qbla\t%0,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -250,7 +250,7 @@
   [(set (match_operand:V2HI 0 "register_operand" "=d")
 	(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 		     UNSPEC_PRECEQU_PH_QBRA))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "precequ.ph.qbra\t%0,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -260,7 +260,7 @@
   [(set (match_operand:V2HI 0 "register_operand" "=d")
 	(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 		     UNSPEC_PRECEU_PH_QBL))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "preceu.ph.qbl\t%0,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -269,7 +269,7 @@
   [(set (match_operand:V2HI 0 "register_operand" "=d")
 	(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 		     UNSPEC_PRECEU_PH_QBR))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "preceu.ph.qbr\t%0,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -278,7 +278,7 @@
   [(set (match_operand:V2HI 0 "register_operand" "=d")
 	(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 		     UNSPEC_PRECEU_PH_QBLA))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "preceu.ph.qbla\t%0,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -287,7 +287,7 @@
   [(set (match_operand:V2HI 0 "register_operand" "=d")
 	(unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 		     UNSPEC_PRECEU_PH_QBRA))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "preceu.ph.qbra\t%0,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -302,7 +302,7 @@
 		       UNSPEC_SHLL))
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL))])]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
 {
   if (which_alternative == 0)
     {
@@ -324,7 +324,7 @@
 		       UNSPEC_SHLL_S))
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL_S))])]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
 {
   if (which_alternative == 0)
     {
@@ -344,7 +344,7 @@
 	(unspec:V4QI [(match_operand:V4QI 1 "register_operand" "d,d")
 		      (match_operand:SI 2 "arith_operand" "I,d")]
 		     UNSPEC_SHRL_QB))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
 {
   if (which_alternative == 0)
     {
@@ -363,7 +363,7 @@
 	(unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d,d")
 		      (match_operand:SI 2 "arith_operand" "I,d")]
 		     UNSPEC_SHRA_PH))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
 {
   if (which_alternative == 0)
     {
@@ -381,7 +381,7 @@
 	(unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d")
 		      (match_operand:SI 2 "arith_operand" "I,d")]
 		     UNSPEC_SHRA_R))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
 {
   if (which_alternative == 0)
     {
@@ -406,7 +406,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBL))
      (clobber (match_scratch:DI 3 "=x"))])]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "muleu_s.ph.qbl\t%0,%1,%2"
   [(set_attr "type"	"imul3")
    (set_attr "mode"	"SI")])
@@ -420,7 +420,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBR))
      (clobber (match_scratch:DI 3 "=x"))])]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "muleu_s.ph.qbr\t%0,%1,%2"
   [(set_attr "type"	"imul3")
    (set_attr "mode"	"SI")])
@@ -435,7 +435,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH))
      (clobber (match_scratch:DI 3 "=x"))])]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "mulq_rs.ph\t%0,%1,%2"
   [(set_attr "type"	"imul3")
    (set_attr "mode"	"SI")])
@@ -450,7 +450,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHL))
      (clobber (match_scratch:DI 3 "=x"))])]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "muleq_s.w.phl\t%0,%1,%2"
   [(set_attr "type"	"imul3")
    (set_attr "mode"	"SI")])
@@ -464,7 +464,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHR))
      (clobber (match_scratch:DI 3 "=x"))])]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "muleq_s.w.phr\t%0,%1,%2"
   [(set_attr "type"	"imul3")
    (set_attr "mode"	"SI")])
@@ -476,7 +476,7 @@
 		    (match_operand:V4QI 2 "register_operand" "d")
 		    (match_operand:V4QI 3 "register_operand" "d")]
 		   UNSPEC_DPAU_H_QBL))]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
   "dpau.h.qbl\t%q0,%2,%3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -487,7 +487,7 @@
 		    (match_operand:V4QI 2 "register_operand" "d")
 		    (match_operand:V4QI 3 "register_operand" "d")]
 		   UNSPEC_DPAU_H_QBR))]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
   "dpau.h.qbr\t%q0,%2,%3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -499,7 +499,7 @@
 		    (match_operand:V4QI 2 "register_operand" "d")
 		    (match_operand:V4QI 3 "register_operand" "d")]
 		   UNSPEC_DPSU_H_QBL))]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
   "dpsu.h.qbl\t%q0,%2,%3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -510,7 +510,7 @@
 		    (match_operand:V4QI 2 "register_operand" "d")
 		    (match_operand:V4QI 3 "register_operand" "d")]
 		   UNSPEC_DPSU_H_QBR))]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
   "dpsu.h.qbr\t%q0,%2,%3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -526,7 +526,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 			UNSPEC_DPAQ_S_W_PH))])]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
   "dpaq_s.w.ph\t%q0,%2,%3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -542,7 +542,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 			UNSPEC_DPSQ_S_W_PH))])]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
   "dpsq_s.w.ph\t%q0,%2,%3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -558,7 +558,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 			UNSPEC_MULSAQ_S_W_PH))])]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
   "mulsaq_s.w.ph\t%q0,%2,%3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -574,7 +574,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 			UNSPEC_DPAQ_SA_L_W))])]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
   "dpaq_sa.l.w\t%q0,%2,%3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -590,7 +590,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 			UNSPEC_DPSQ_SA_L_W))])]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
   "dpsq_sa.l.w\t%q0,%2,%3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -606,7 +606,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 			UNSPEC_MAQ_S_W_PHL))])]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
   "maq_s.w.phl\t%q0,%2,%3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -621,7 +621,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 			UNSPEC_MAQ_S_W_PHR))])]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
   "maq_s.w.phr\t%q0,%2,%3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -637,7 +637,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 			UNSPEC_MAQ_SA_W_PHL))])]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
   "maq_sa.w.phl\t%q0,%2,%3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -652,7 +652,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 			UNSPEC_MAQ_SA_W_PHR))])]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
   "maq_sa.w.phr\t%q0,%2,%3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -663,7 +663,7 @@
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(unspec:SI [(match_operand:SI 1 "register_operand" "d")]
 		   UNSPEC_BITREV))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "bitrev\t%0,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -676,7 +676,7 @@
 		    (reg:CCDSP CCDSP_SC_REGNUM)
 		    (reg:CCDSP CCDSP_PO_REGNUM)]
 		   UNSPEC_INSV))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "insv\t%0,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -686,7 +686,7 @@
   [(set (match_operand:V4QI 0 "register_operand" "=d,d")
 	(unspec:V4QI [(match_operand:SI 1 "arith_operand" "I,d")]
 		     UNSPEC_REPL_QB))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
 {
   if (which_alternative == 0)
     {
@@ -703,7 +703,7 @@
   [(set (match_operand:V2HI 0 "register_operand" "=d,d")
 	(unspec:V2HI [(match_operand:SI 1 "reg_imm10_operand" "YB,d")]
 		     UNSPEC_REPL_PH))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "@
    repl.ph\t%0,%1
    replv.ph\t%0,%1"
@@ -718,7 +718,7 @@
 		       (match_operand:DSPV 1 "register_operand" "d")
 		       (reg:CCDSP CCDSP_CC_REGNUM)]
 		      UNSPEC_CMP_EQ))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "cmp<DSPV:dspfmt1_1>.eq.<DSPV:dspfmt2>\t%0,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -729,7 +729,7 @@
 		       (match_operand:DSPV 1 "register_operand" "d")
 		       (reg:CCDSP CCDSP_CC_REGNUM)]
 		      UNSPEC_CMP_LT))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "cmp<DSPV:dspfmt1_1>.lt.<DSPV:dspfmt2>\t%0,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -740,7 +740,7 @@
 		       (match_operand:DSPV 1 "register_operand" "d")
 		       (reg:CCDSP CCDSP_CC_REGNUM)]
 		      UNSPEC_CMP_LE))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "cmp<DSPV:dspfmt1_1>.le.<DSPV:dspfmt2>\t%0,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -750,7 +750,7 @@
 	(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
 		    (match_operand:V4QI 2 "register_operand" "d")]
 		   UNSPEC_CMPGU_EQ_QB))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "cmpgu.eq.qb\t%0,%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -760,7 +760,7 @@
 	(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
 		    (match_operand:V4QI 2 "register_operand" "d")]
 		   UNSPEC_CMPGU_LT_QB))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "cmpgu.lt.qb\t%0,%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -770,7 +770,7 @@
 	(unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
 		    (match_operand:V4QI 2 "register_operand" "d")]
 		   UNSPEC_CMPGU_LE_QB))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "cmpgu.le.qb\t%0,%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -782,7 +782,7 @@
 		      (match_operand:DSPV 2 "register_operand" "d")
 		      (reg:CCDSP CCDSP_CC_REGNUM)]
 		     UNSPEC_PICK))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "pick.<DSPV:dspfmt2>\t%0,%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -793,7 +793,7 @@
 	(unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
 		      (match_operand:V2HI 2 "register_operand" "d")]
 		     UNSPEC_PACKRL_PH))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "packrl.ph\t%0,%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -808,7 +808,7 @@
 		     UNSPEC_EXTR_W))
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_W))])]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
 {
   if (which_alternative == 0)
     {
@@ -829,7 +829,7 @@
 		     UNSPEC_EXTR_R_W))
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_R_W))])]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
 {
   if (which_alternative == 0)
     {
@@ -850,7 +850,7 @@
 		     UNSPEC_EXTR_RS_W))
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_RS_W))])]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
 {
   if (which_alternative == 0)
     {
@@ -872,7 +872,7 @@
 		     UNSPEC_EXTR_S_H))
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_S_H))])]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
 {
   if (which_alternative == 0)
     {
@@ -895,7 +895,7 @@
 		     UNSPEC_EXTP))
      (set (reg:CCDSP CCDSP_EF_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTP))])]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
 {
   if (which_alternative == 0)
     {
@@ -920,7 +920,7 @@
 			 (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTPDP))
      (set (reg:CCDSP CCDSP_EF_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTPDP))])]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
 {
   if (which_alternative == 0)
     {
@@ -939,7 +939,7 @@
 	(unspec:DI [(match_operand:DI 1 "register_operand" "0,0")
 		    (match_operand:SI 2 "arith_operand" "I,d")]
 		   UNSPEC_SHILO))]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
 {
   if (which_alternative == 0)
     {
@@ -963,7 +963,7 @@
      (set (reg:CCDSP CCDSP_PO_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)
 			 (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))])]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
   "mthlip\t%2,%q0"
   [(set_attr "type"	"mfhilo")
    (set_attr "mode"	"SI")])
@@ -985,7 +985,7 @@
 	  (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
      (set (reg:CCDSP CCDSP_EF_REGNUM)
 	  (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))])]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "wrdsp\t%0,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -1001,7 +1001,7 @@
 		    (reg:CCDSP CCDSP_CC_REGNUM)
 		    (reg:CCDSP CCDSP_EF_REGNUM)]
 		   UNSPEC_RDDSP))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "rddsp\t%0,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -1014,7 +1014,7 @@
 					  "register_operand" "d")
 					 (match_operand:SI 2
 					  "register_operand" "d")))))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "lbux\t%0,%2(%1)"
   [(set_attr "type"	"load")
    (set_attr "mode"	"SI")
@@ -1026,7 +1026,7 @@
 					  "register_operand" "d")
 					 (match_operand:SI 2
 					  "register_operand" "d")))))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "lhx\t%0,%2(%1)"
   [(set_attr "type"	"load")
    (set_attr "mode"	"SI")
@@ -1036,7 +1036,7 @@
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d")
 			 (match_operand:SI 2 "register_operand" "d"))))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "lwx\t%0,%2(%1)"
   [(set_attr "type"	"load")
    (set_attr "mode"	"SI")
@@ -1050,7 +1050,7 @@
 			  (match_operand:SI 0 "immediate_operand" "I"))
 		      (label_ref (match_operand 1 "" ""))
 		      (pc)))]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "%*bposge%0\t%1%/"
   [(set_attr "type"	"branch")
    (set_attr "mode"	"none")])
diff --git a/gcc/config/mips/mips-dspr2.md b/gcc/config/mips/mips-dspr2.md
index 2019008..3cde900 100644
--- a/gcc/config/mips/mips-dspr2.md
+++ b/gcc/config/mips/mips-dspr2.md
@@ -7,7 +7,7 @@
 		       UNSPEC_ABSQ_S_QB))
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))])]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "absq_s.qb\t%0,%z1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -19,7 +19,7 @@
 		     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")))
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))])]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "addu.ph\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -32,7 +32,7 @@
 		       UNSPEC_ADDU_S_PH))
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))])]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "addu_s.ph\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -42,7 +42,7 @@
 	(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 		      (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 		     UNSPEC_ADDUH_QB))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "adduh.qb\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -52,7 +52,7 @@
 	(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 		      (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 		     UNSPEC_ADDUH_R_QB))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "adduh_r.qb\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -63,7 +63,7 @@
 		    (match_operand:SI 2 "reg_or_0_operand" "dJ")
 		    (match_operand:SI 3 "const_int_operand" "n")]
 		   UNSPEC_APPEND))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
 {
   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
@@ -78,7 +78,7 @@
 		    (match_operand:SI 2 "reg_or_0_operand" "dJ")
 		    (match_operand:SI 3 "const_int_operand" "n")]
 		   UNSPEC_BALIGN))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
 {
   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 3)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 3);
@@ -97,7 +97,7 @@
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)
 			 (reg:CCDSP CCDSP_CC_REGNUM)]
 			UNSPEC_CMPGDU_EQ_QB))])]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "cmpgdu.eq.qb\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -112,7 +112,7 @@
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)
 			 (reg:CCDSP CCDSP_CC_REGNUM)]
 			UNSPEC_CMPGDU_LT_QB))])]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "cmpgdu.lt.qb\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -127,7 +127,7 @@
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)
 			 (reg:CCDSP CCDSP_CC_REGNUM)]
 			UNSPEC_CMPGDU_LE_QB))])]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "cmpgdu.le.qb\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -138,7 +138,7 @@
 		    (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 		    (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 		   UNSPEC_DPA_W_PH))]
-  "TARGET_DSPR2 && !TARGET_64BIT"
+  "ISA_HAS_DSPR2 && !TARGET_64BIT"
   "dpa.w.ph\t%q0,%z2,%z3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -149,7 +149,7 @@
 		    (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 		    (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 		   UNSPEC_DPS_W_PH))]
-  "TARGET_DSPR2 && !TARGET_64BIT"
+  "ISA_HAS_DSPR2 && !TARGET_64BIT"
   "dps.w.ph\t%q0,%z2,%z3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -160,7 +160,7 @@
 	 (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
 		  (any_extend:DI (match_operand:SI 3 "register_operand")))
 	 (match_operand:DI 1 "register_operand")))]
-  "TARGET_DSPR2 && !TARGET_64BIT")
+  "ISA_HAS_DSPR2 && !TARGET_64BIT")
 
 (define_expand "mips_msub<u>"
   [(set (match_operand:DI 0 "register_operand")
@@ -168,7 +168,7 @@
 	 (match_operand:DI 1 "register_operand")
 	 (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
 		  (any_extend:DI (match_operand:SI 3 "register_operand")))))]
-  "TARGET_DSPR2 && !TARGET_64BIT")
+  "ISA_HAS_DSPR2 && !TARGET_64BIT")
 
 (define_insn "mulv2hi3"
   [(parallel
@@ -178,7 +178,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_PH))
      (clobber (match_scratch:DI 3 "=x"))])]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "mul.ph\t%0,%1,%2"
   [(set_attr "type"	"imul3")
    (set_attr "mode"	"SI")])
@@ -192,7 +192,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_S_PH))
      (clobber (match_scratch:DI 3 "=x"))])]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "mul_s.ph\t%0,%z1,%z2"
   [(set_attr "type"	"imul3")
    (set_attr "mode"	"SI")])
@@ -206,7 +206,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_W))
      (clobber (match_scratch:DI 3 "=x"))])]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "mulq_rs.w\t%0,%z1,%z2"
   [(set_attr "type"	"imul3")
    (set_attr "mode"	"SI")])
@@ -220,7 +220,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_PH))
      (clobber (match_scratch:DI 3 "=x"))])]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "mulq_s.ph\t%0,%z1,%z2"
   [(set_attr "type"	"imul3")
    (set_attr "mode"	"SI")])
@@ -234,7 +234,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_W))
      (clobber (match_scratch:DI 3 "=x"))])]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "mulq_s.w\t%0,%z1,%z2"
   [(set_attr "type"	"imul3")
    (set_attr "mode"	"SI")])
@@ -245,7 +245,7 @@
 		    (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 		    (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 		   UNSPEC_MULSA_W_PH))]
-  "TARGET_DSPR2 && !TARGET_64BIT"
+  "ISA_HAS_DSPR2 && !TARGET_64BIT"
   "mulsa.w.ph\t%q0,%z2,%z3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -255,7 +255,7 @@
 	(mult:DI
 	 (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
 	 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
-  "TARGET_DSPR2 && !TARGET_64BIT"
+  "ISA_HAS_DSPR2 && !TARGET_64BIT"
   "mult\t%q0,%1,%2"
   [(set_attr "type"	"imul")
    (set_attr "mode"	"SI")])
@@ -265,7 +265,7 @@
 	(mult:DI
 	 (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
 	 (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
-  "TARGET_DSPR2 && !TARGET_64BIT"
+  "ISA_HAS_DSPR2 && !TARGET_64BIT"
   "multu\t%q0,%1,%2"
   [(set_attr "type"	"imul")
    (set_attr "mode"	"SI")])
@@ -275,7 +275,7 @@
 	(unspec:V4QI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 		      (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 		     UNSPEC_PRECR_QB_PH))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "precr.qb.ph\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -286,7 +286,7 @@
 		      (match_operand:SI 2 "reg_or_0_operand" "dJ")
 		      (match_operand:SI 3 "const_int_operand" "n")]
 		     UNSPEC_PRECR_SRA_PH_W))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
 {
   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
@@ -301,7 +301,7 @@
 		      (match_operand:SI 2 "reg_or_0_operand" "dJ")
 		      (match_operand:SI 3 "const_int_operand" "n")]
 		     UNSPEC_PRECR_SRA_R_PH_W))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
 {
   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
@@ -316,7 +316,7 @@
 		    (match_operand:SI 2 "reg_or_0_operand" "dJ")
 		    (match_operand:SI 3 "const_int_operand" "n")]
 		   UNSPEC_PREPEND))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
 {
   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
@@ -330,7 +330,7 @@
 	(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
 		      (match_operand:SI 2 "arith_operand" "I,d")]
 		     UNSPEC_SHRA_QB))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
 {
   if (which_alternative == 0)
     {
@@ -349,7 +349,7 @@
 	(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
 		      (match_operand:SI 2 "arith_operand" "I,d")]
 		     UNSPEC_SHRA_R_QB))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
 {
   if (which_alternative == 0)
     {
@@ -367,7 +367,7 @@
 	(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG,dYG")
 		      (match_operand:SI 2 "arith_operand" "I,d")]
 		     UNSPEC_SHRL_PH))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
 {
   if (which_alternative == 0)
     {
@@ -388,7 +388,7 @@
 		       UNSPEC_SUBU_PH))
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))])]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "subu.ph\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -401,7 +401,7 @@
 		       UNSPEC_SUBU_S_PH))
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))])]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "subu_s.ph\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -411,7 +411,7 @@
 	(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 		      (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 		     UNSPEC_SUBUH_QB))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "subuh.qb\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -421,7 +421,7 @@
 	(unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 		      (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 		     UNSPEC_SUBUH_R_QB))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "subuh_r.qb\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -431,7 +431,7 @@
 	(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 		      (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 		     UNSPEC_ADDQH_PH))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "addqh.ph\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -441,7 +441,7 @@
 	(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 		      (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 		     UNSPEC_ADDQH_R_PH))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "addqh_r.ph\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -451,7 +451,7 @@
 	(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 		    (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 		   UNSPEC_ADDQH_W))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "addqh.w\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -461,7 +461,7 @@
 	(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 		    (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 		   UNSPEC_ADDQH_R_W))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "addqh_r.w\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -471,7 +471,7 @@
 	(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 		      (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 		     UNSPEC_SUBQH_PH))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "subqh.ph\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -481,7 +481,7 @@
 	(unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 		      (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 		     UNSPEC_SUBQH_R_PH))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "subqh_r.ph\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -491,7 +491,7 @@
 	(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 		    (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 		   UNSPEC_SUBQH_W))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "subqh.w\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -501,7 +501,7 @@
 	(unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 		    (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 		   UNSPEC_SUBQH_R_W))]
-  "TARGET_DSPR2"
+  "ISA_HAS_DSPR2"
   "subqh_r.w\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
@@ -512,7 +512,7 @@
 		    (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 		    (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 		   UNSPEC_DPAX_W_PH))]
-  "TARGET_DSPR2 && !TARGET_64BIT"
+  "ISA_HAS_DSPR2 && !TARGET_64BIT"
   "dpax.w.ph\t%q0,%z2,%z3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -523,7 +523,7 @@
 		    (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 		    (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 		   UNSPEC_DPSX_W_PH))]
-  "TARGET_DSPR2 && !TARGET_64BIT"
+  "ISA_HAS_DSPR2 && !TARGET_64BIT"
   "dpsx.w.ph\t%q0,%z2,%z3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -538,7 +538,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 			UNSPEC_DPAQX_S_W_PH))])]
-  "TARGET_DSPR2 && !TARGET_64BIT"
+  "ISA_HAS_DSPR2 && !TARGET_64BIT"
   "dpaqx_s.w.ph\t%q0,%z2,%z3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -553,7 +553,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 			UNSPEC_DPAQX_SA_W_PH))])]
-  "TARGET_DSPR2 && !TARGET_64BIT"
+  "ISA_HAS_DSPR2 && !TARGET_64BIT"
   "dpaqx_sa.w.ph\t%q0,%z2,%z3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -568,7 +568,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 			UNSPEC_DPSQX_S_W_PH))])]
-  "TARGET_DSPR2 && !TARGET_64BIT"
+  "ISA_HAS_DSPR2 && !TARGET_64BIT"
   "dpsqx_s.w.ph\t%q0,%z2,%z3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
@@ -583,7 +583,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 			UNSPEC_DPSQX_SA_W_PH))])]
-  "TARGET_DSPR2 && !TARGET_64BIT"
+  "ISA_HAS_DSPR2 && !TARGET_64BIT"
   "dpsqx_sa.w.ph\t%q0,%z2,%z3"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
diff --git a/gcc/config/mips/mips-fixed.md b/gcc/config/mips/mips-fixed.md
index 3305be8..758df26 100644
--- a/gcc/config/mips/mips-fixed.md
+++ b/gcc/config/mips/mips-fixed.md
@@ -13,15 +13,15 @@
 			     (V2HQ "ph") (V2HA "ph")])
 
 ;; For unsigned add/sub with saturation
-(define_mode_iterator UADDSUB [(UQQ "TARGET_DSP") (UHQ "TARGET_DSPR2")
-			       (UHA "TARGET_DSPR2") (V4UQQ "TARGET_DSP")
-			       (V2UHQ "TARGET_DSPR2") (V2UHA "TARGET_DSPR2")])
+(define_mode_iterator UADDSUB [(UQQ "ISA_HAS_DSP") (UHQ "ISA_HAS_DSPR2")
+			       (UHA "ISA_HAS_DSPR2") (V4UQQ "ISA_HAS_DSP")
+			       (V2UHQ "ISA_HAS_DSPR2") (V2UHA "ISA_HAS_DSPR2")])
 (define_mode_attr uaddsubfmt [(UQQ "qb") (UHQ "ph") (UHA "ph")
 			      (V4UQQ "qb") (V2UHQ "ph") (V2UHA "ph")])
 
 ;; For signed multiplication with saturation
-(define_mode_iterator MULQ [(V2HQ "TARGET_DSP") (HQ "TARGET_DSP")
-			    (SQ "TARGET_DSPR2")])
+(define_mode_iterator MULQ [(V2HQ "ISA_HAS_DSP") (HQ "ISA_HAS_DSP")
+			    (SQ "ISA_HAS_DSPR2")])
 (define_mode_attr mulqfmt [(V2HQ "ph") (HQ "ph") (SQ "w")])
 
 (define_insn "add<mode>3"
@@ -52,7 +52,7 @@
 			  (match_operand:ADDSUB 2 "register_operand" "d")))
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "addq_s.<addsubfmt>\t%0,%1,%2"
   [(set_attr "type" "arith")
    (set_attr "mode" "<IMODE>")])
@@ -85,7 +85,7 @@
 			   (match_operand:ADDSUB 2 "register_operand" "d")))
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
-  "TARGET_DSP"
+  "ISA_HAS_DSP"
   "subq_s.<addsubfmt>\t%0,%1,%2"
   [(set_attr "type" "arith")
    (set_attr "mode" "<IMODE>")])
@@ -115,7 +115,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 			UNSPEC_DPAQ_SA_L_W))])]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
   "dpaq_sa.l.w\t%q0,%1,%2"
   [(set_attr "type" "imadd")
    (set_attr "mode" "SI")])
@@ -132,7 +132,7 @@
      (set (reg:CCDSP CCDSP_OU_REGNUM)
 	  (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 			UNSPEC_DPSQ_SA_L_W))])]
-  "TARGET_DSP && !TARGET_64BIT"
+  "ISA_HAS_DSP && !TARGET_64BIT"
   "dpsq_sa.l.w\t%q0,%1,%2"
   [(set_attr "type" "imadd")
    (set_attr "mode" "SI")])
diff --git a/gcc/config/mips/mips-ps-3d.md b/gcc/config/mips/mips-ps-3d.md
index 36cc4c1..63ec16b 100644
--- a/gcc/config/mips/mips-ps-3d.md
+++ b/gcc/config/mips/mips-ps-3d.md
@@ -25,7 +25,7 @@
 			  (const_int 0)])
 	 (match_operand:V2SF 2 "register_operand" "f,0")
 	 (match_operand:V2SF 3 "register_operand" "0,f")))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "@
     mov%T4.ps\t%0,%2,%1
     mov%t4.ps\t%0,%3,%1"
@@ -38,7 +38,7 @@
 		      (match_operand:V2SF 2 "register_operand" "0,f")
 		      (match_operand:CCV2 3 "register_operand" "z,z")]
 		     UNSPEC_MOVE_TF_PS))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "@
     movt.ps\t%0,%1,%3
     movf.ps\t%0,%2,%3"
@@ -51,7 +51,7 @@
 	(if_then_else:V2SF (match_dup 5)
 			   (match_operand:V2SF 2 "register_operand")
 			   (match_operand:V2SF 3 "register_operand")))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
 {
   /* We can only support MOVN.PS and MOVZ.PS.
      NOTE: MOVT.PS and MOVF.PS have different semantics from MOVN.PS and 
@@ -72,7 +72,7 @@
 	 (match_operand:V2SF 1 "register_operand" "f")
 	 (match_operand:V2SF 2 "register_operand" "f")
 	 (const_int 2)))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "pul.ps\t%0,%1,%2"
   [(set_attr "type" "fmove")
    (set_attr "mode" "SF")])
@@ -86,7 +86,7 @@
 			  (parallel [(const_int 1)
 				     (const_int 0)]))
 	 (const_int 2)))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "puu.ps\t%0,%1,%2"
   [(set_attr "type" "fmove")
    (set_attr "mode" "SF")])
@@ -100,7 +100,7 @@
 				     (const_int 0)]))
 	 (match_operand:V2SF 2 "register_operand" "f")
 	 (const_int 2)))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "pll.ps\t%0,%1,%2"
   [(set_attr "type" "fmove")
    (set_attr "mode" "SF")])
@@ -116,7 +116,7 @@
 			  (parallel [(const_int 1)
 				     (const_int 0)]))
 	 (const_int 2)))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "plu.ps\t%0,%1,%2"
   [(set_attr "type" "fmove")
    (set_attr "mode" "SF")])
@@ -125,7 +125,7 @@
 (define_expand "vec_initv2sf"
   [(match_operand:V2SF 0 "register_operand")
    (match_operand:V2SF 1 "")]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
 {
   rtx op0 = force_reg (SFmode, XVECEXP (operands[1], 0, 0));
   rtx op1 = force_reg (SFmode, XVECEXP (operands[1], 0, 1));
@@ -138,7 +138,7 @@
 	(vec_concat:V2SF
 	 (match_operand:SF 1 "register_operand" "f")
 	 (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
 {
   if (BYTES_BIG_ENDIAN)
     return "cvt.ps.s\t%0,%1,%2";
@@ -157,7 +157,7 @@
 	(vec_select:SF (match_operand:V2SF 1 "register_operand" "f")
 		       (parallel
 			[(match_operand 2 "const_0_or_1_operand" "")])))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
 {
   if (INTVAL (operands[2]) == !BYTES_BIG_ENDIAN)
     return "cvt.s.pu\t%0,%1";
@@ -174,7 +174,7 @@
   [(match_operand:V2SF 0 "register_operand")
    (match_operand:SF 1 "register_operand")
    (match_operand 2 "const_0_or_1_operand")]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
 {
   rtx temp;
 
@@ -194,7 +194,7 @@
   [(match_operand:V2SF 0 "register_operand")
    (match_operand:SF 1 "register_operand")
    (match_operand:SF 2 "register_operand")]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
 {
   if (BYTES_BIG_ENDIAN)
     emit_insn (gen_vec_initv2sf_internal (operands[0], operands[1],
@@ -210,7 +210,7 @@
   [(set (match_operand:SF 0 "register_operand")
 	(vec_select:SF (match_operand:V2SF 1 "register_operand")
 		       (parallel [(match_dup 2)])))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   { operands[2] = GEN_INT (BYTES_BIG_ENDIAN); })
 
 ; cvt.s.pu - Floating Point Convert Pair Upper to Single Floating Point
@@ -218,7 +218,7 @@
   [(set (match_operand:SF 0 "register_operand")
 	(vec_select:SF (match_operand:V2SF 1 "register_operand")
 		       (parallel [(match_dup 2)])))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   { operands[2] = GEN_INT (!BYTES_BIG_ENDIAN); })
 
 ; alnv.ps - Floating Point Align Variable
@@ -228,7 +228,7 @@
 		      (match_operand:V2SF 2 "register_operand" "f")
 		      (match_operand:SI 3 "register_operand" "d")]
 		     UNSPEC_ALNV_PS))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "alnv.ps\t%0,%1,%2,%3"
   [(set_attr "type" "fmove")
    (set_attr "mode" "SF")])
@@ -239,7 +239,7 @@
 	(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
 		      (match_operand:V2SF 2 "register_operand" "f")]
 		     UNSPEC_ADDR_PS))]
-  "TARGET_MIPS3D"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "addr.ps\t%0,%1,%2"
   [(set_attr "type" "fadd")
    (set_attr "mode" "SF")])
@@ -249,7 +249,7 @@
   [(set (match_operand:V2SF 0 "register_operand" "=f")
 	(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
 		     UNSPEC_CVT_PW_PS))]
-  "TARGET_MIPS3D"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "cvt.pw.ps\t%0,%1"
   [(set_attr "type" "fcvt")
    (set_attr "mode" "SF")])
@@ -259,7 +259,7 @@
   [(set (match_operand:V2SF 0 "register_operand" "=f")
 	(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
 		     UNSPEC_CVT_PS_PW))]
-  "TARGET_MIPS3D"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "cvt.ps.pw\t%0,%1"
   [(set_attr "type" "fcvt")
    (set_attr "mode" "SF")])
@@ -270,7 +270,7 @@
 	(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")
 		      (match_operand:V2SF 2 "register_operand" "f")]
 		     UNSPEC_MULR_PS))]
-  "TARGET_MIPS3D"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "mulr.ps\t%0,%1,%2"
   [(set_attr "type" "fmul")
    (set_attr "mode" "SF")])
@@ -280,7 +280,7 @@
   [(set (match_operand:V2SF 0 "register_operand")
 	(unspec:V2SF [(match_operand:V2SF 1 "register_operand")]
 		     UNSPEC_ABS_PS))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
 {
   /* If we can ignore NaNs, this operation is equivalent to the
      rtl ABS code.  */
@@ -295,7 +295,7 @@
   [(set (match_operand:V2SF 0 "register_operand" "=f")
 	(unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")]
 		     UNSPEC_ABS_PS))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "abs.ps\t%0,%1"
   [(set_attr "type" "fabs")
    (set_attr "mode" "SF")])
@@ -310,7 +310,7 @@
 		    (match_operand:SCALARF 2 "register_operand" "f")
 		    (match_operand 3 "const_int_operand" "")]
 		   UNSPEC_CABS))]
-  "TARGET_MIPS3D"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "cabs.%Y3.<fmt>\t%0,%1,%2"
   [(set_attr "type" "fcmp")
    (set_attr "mode" "FPSW")])
@@ -328,7 +328,7 @@
 		      (match_operand:V2SF 4 "register_operand" "f")
 		      (match_operand 5 "const_int_operand" "")]
 		     UNSPEC_C))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "#"
   "&& reload_completed"
   [(set (match_dup 6)
@@ -357,7 +357,7 @@
 		      (match_operand:V2SF 4 "register_operand" "f")
 		      (match_operand 5 "const_int_operand" "")]
 		     UNSPEC_CABS))]
-  "TARGET_MIPS3D"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "#"
   "&& reload_completed"
   [(set (match_dup 6)
@@ -389,7 +389,7 @@
 		      (match_operand:V2SF 2 "register_operand" "f")
 		      (match_operand 3 "const_int_operand" "")]
 		     UNSPEC_C))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "c.%Y3.ps\t%0,%1,%2"
   [(set_attr "type" "fcmp")
    (set_attr "mode" "FPSW")])
@@ -400,7 +400,7 @@
 		      (match_operand:V2SF 2 "register_operand" "f")
 		      (match_operand 3 "const_int_operand" "")]
 		     UNSPEC_CABS))]
-  "TARGET_MIPS3D"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "cabs.%Y3.ps\t%0,%1,%2"
   [(set_attr "type" "fcmp")
    (set_attr "mode" "FPSW")])
@@ -416,7 +416,7 @@
 	   [(fcond (match_operand:V2SF 1 "register_operand" "f")
 		   (match_operand:V2SF 2 "register_operand" "f"))]
 	   UNSPEC_SCC))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "c.<fcond>.ps\t%0,%1,%2"
   [(set_attr "type" "fcmp")
    (set_attr "mode" "FPSW")])
@@ -427,7 +427,7 @@
 	   [(swapped_fcond (match_operand:V2SF 1 "register_operand" "f")
 			   (match_operand:V2SF 2 "register_operand" "f"))]
 	   UNSPEC_SCC))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "c.<swapped_fcond>.ps\t%0,%2,%1"
   [(set_attr "type" "fcmp")
    (set_attr "mode" "FPSW")])
@@ -443,7 +443,7 @@
 			  (const_int 0))
 		      (label_ref (match_operand 1 "" ""))
 		      (pc)))]
-  "TARGET_MIPS3D"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "%*bc1any4t\t%0,%1%/"
   [(set_attr "type" "branch")
    (set_attr "mode" "none")])
@@ -455,7 +455,7 @@
 			  (const_int -1))
 		      (label_ref (match_operand 1 "" ""))
 		      (pc)))]
-  "TARGET_MIPS3D"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "%*bc1any4f\t%0,%1%/"
   [(set_attr "type" "branch")
    (set_attr "mode" "none")])
@@ -467,7 +467,7 @@
 			  (const_int 0))
 		      (label_ref (match_operand 1 "" ""))
 		      (pc)))]
-  "TARGET_MIPS3D"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "%*bc1any2t\t%0,%1%/"
   [(set_attr "type" "branch")
    (set_attr "mode" "none")])
@@ -479,7 +479,7 @@
 			  (const_int -1))
 		      (label_ref (match_operand 1 "" ""))
 		      (pc)))]
-  "TARGET_MIPS3D"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "%*bc1any2f\t%0,%1%/"
   [(set_attr "type" "branch")
    (set_attr "mode" "none")])
@@ -545,7 +545,7 @@
   [(set (match_operand:ANYF 0 "register_operand" "=f")
 	(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
 		     UNSPEC_RSQRT1))]
-  "TARGET_MIPS3D"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "rsqrt1.<fmt>\t%0,%1"
   [(set_attr "type" "frsqrt1")
    (set_attr "mode" "<UNITMODE>")])
@@ -555,7 +555,7 @@
 	(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")
 		      (match_operand:ANYF 2 "register_operand" "f")]
 		     UNSPEC_RSQRT2))]
-  "TARGET_MIPS3D"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "rsqrt2.<fmt>\t%0,%1,%2"
   [(set_attr "type" "frsqrt2")
    (set_attr "mode" "<UNITMODE>")])
@@ -564,7 +564,7 @@
   [(set (match_operand:ANYF 0 "register_operand" "=f")
 	(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
 		     UNSPEC_RECIP1))]
-  "TARGET_MIPS3D"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "recip1.<fmt>\t%0,%1"
   [(set_attr "type" "frdiv1")
    (set_attr "mode" "<UNITMODE>")])
@@ -574,7 +574,7 @@
 	(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")
 		      (match_operand:ANYF 2 "register_operand" "f")]
 		     UNSPEC_RECIP2))]
-  "TARGET_MIPS3D"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "recip2.<fmt>\t%0,%1,%2"
   [(set_attr "type" "frdiv2")
    (set_attr "mode" "<UNITMODE>")])
@@ -587,7 +587,7 @@
 	     (match_operand:V2SF 5 "register_operand")])
 	  (match_operand:V2SF 1 "register_operand")
 	  (match_operand:V2SF 2 "register_operand")))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
 {
   mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
 			 GET_CODE (operands[3]), operands[4], operands[5]);
@@ -598,7 +598,7 @@
   [(set (match_operand:V2SF 0 "register_operand")
 	(smin:V2SF (match_operand:V2SF 1 "register_operand")
 		   (match_operand:V2SF 2 "register_operand")))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
 {
   mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
 			 LE, operands[1], operands[2]);
@@ -609,7 +609,7 @@
   [(set (match_operand:V2SF 0 "register_operand")
 	(smax:V2SF (match_operand:V2SF 1 "register_operand")
 		   (match_operand:V2SF 2 "register_operand")))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
 {
   mips_expand_vcondv2sf (operands[0], operands[1], operands[2],
 			 LE, operands[2], operands[1]);
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index f2c8ba9..1d72056 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -5696,10 +5696,6 @@ mips_set_mips16_mode (int mips16_p)
 	 we use a %gprel() operator.  */
       target_flags &= ~MASK_EXPLICIT_RELOCS;
 
-      /* Silently disable DSP extensions.  */
-      target_flags &= ~MASK_DSP;
-      target_flags &= ~MASK_DSPR2;
-
       /* Experiments suggest we get the best overall results from using
 	 the range of an unextended lw or sw.  Code that makes heavy use
 	 of byte or short accesses can do better with ranges of 0...31
@@ -6151,8 +6147,8 @@ override_options (void)
     target_flags |= MASK_PAIRED_SINGLE_FLOAT;
 
   /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
-     and TARGET_HARD_FLOAT are both true.  */
-  if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
+     and TARGET_HARD_FLOAT_ABI are both true.  */
+  if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
     error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
 
   /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
@@ -6351,7 +6347,7 @@ mips_swap_registers (unsigned int i)
 void
 mips_conditional_register_usage (void)
 {
-  if (!TARGET_DSP)
+  if (!ISA_HAS_DSP)
     {
       int regno;
 
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index d38bba8..169779c 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -879,6 +879,12 @@ extern enum mips_llsc_setting mips_llsc;
 /* ISA has lwxs instruction (load w/scaled index address.  */
 #define ISA_HAS_LWXS		(TARGET_SMARTMIPS && !TARGET_MIPS16)
 
+/* The DSP ASE is available.  */
+#define ISA_HAS_DSP		(TARGET_DSP && !TARGET_MIPS16)
+
+/* Revision 2 of the DSP ASE is available.  */
+#define ISA_HAS_DSPR2		(TARGET_DSPR2 && !TARGET_MIPS16)
+
 /* True if the result of a load is not available to the next instruction.
    A nop will then be needed between instructions like "lw $4,..."
    and "addiu $4,$4,1".  */
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index efd57c9..92d5ab2 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -492,7 +492,7 @@
 ;; floating-point mode is allowed.
 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
 			    (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
-			    (V2SF "TARGET_PAIRED_SINGLE_FLOAT")])
+			    (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
 
 ;; Like ANYF, but only applies to scalar modes.
 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
@@ -1035,7 +1035,7 @@
   [(set (match_operand:V2SF 0 "register_operand" "=f")
 	(mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
 		   (match_operand:V2SF 2 "register_operand" "f")))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
   "mul.ps\t%0,%1,%2"
   [(set_attr "type" "fmul")
    (set_attr "mode" "SF")])
@@ -1581,7 +1581,7 @@
   [(set (match_operand:DI 0 "register_operand" "=x")
 	(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
 		 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
-  "!TARGET_64BIT && !TARGET_FIX_R4000 && !TARGET_DSPR2"
+  "!TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DSPR2"
   "mult<u>\t%1,%2"
   [(set_attr "type" "imul")
    (set_attr "mode" "SI")])
@@ -1678,9 +1678,9 @@
 	   (mult:DI
 	      (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
 	      (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
-  "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || TARGET_DSPR2)"
+  "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)"
 {
-  if (TARGET_DSPR2)
+  if (ISA_HAS_DSPR2)
     return "msub<u>\t%q0,%1,%2";
   else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
     return "msub<u>\t%1,%2";
@@ -1797,12 +1797,12 @@
 	 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
 		  (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
 	 (match_operand:DI 3 "register_operand" "0")))]
-  "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || TARGET_DSPR2)
+  "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)
    && !TARGET_64BIT"
 {
   if (TARGET_MAD)
     return "mad<u>\t%1,%2";
-  else if (TARGET_DSPR2)
+  else if (ISA_HAS_DSPR2)
     return "madd<u>\t%q0,%1,%2";
   else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
     return "madd<u>\t%1,%2";
@@ -4043,7 +4043,7 @@
 (define_expand "movv2sf"
   [(set (match_operand:V2SF 0)
 	(match_operand:V2SF 1))]
-  "TARGET_PAIRED_SINGLE_FLOAT"
+  "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
 {
   if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
     DONE;
@@ -4052,8 +4052,9 @@
 (define_insn "movv2sf_hardfloat_64bit"
   [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
 	(match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
-  "TARGET_PAIRED_SINGLE_FLOAT
+  "TARGET_HARD_FLOAT
    && TARGET_64BIT
+   && TARGET_PAIRED_SINGLE_FLOAT
    && (register_operand (operands[0], V2SFmode)
        || reg_or_0_operand (operands[1], V2SFmode))"
   { return mips_output_move (operands[0], operands[1]); }