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author | liuhongt <hongtao.liu@intel.com> | 2021-12-15 13:07:30 +0800 |
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committer | liuhongt <hongtao.liu@intel.com> | 2021-12-20 09:53:06 +0800 |
commit | 19dcecd963295b02b96c8cac57933657dbe3234a (patch) | |
tree | d750ed039f56a051d1071027fd88f18523001816 /gcc/config | |
parent | 29309f6e29d0912eececa1bac29b249440469107 (diff) | |
download | gcc-19dcecd963295b02b96c8cac57933657dbe3234a.zip gcc-19dcecd963295b02b96c8cac57933657dbe3234a.tar.gz gcc-19dcecd963295b02b96c8cac57933657dbe3234a.tar.bz2 |
Optimize bit_and op1 float_vector_all_ones_operands to op1.
gcc/ChangeLog:
PR target/98468
* config/i386/sse.md (*bit_and_float_vector_all_ones): New
pre-reload splitter.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr98468.c: New test.
Diffstat (limited to 'gcc/config')
-rw-r--r-- | gcc/config/i386/sse.md | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 827ffbb..5196149 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4465,6 +4465,18 @@ (const_string "<sseinsnmode>") (const_string "XI")))]) +;; Generic part doesn't support the simpliciation of logic operation with +;; float_vector_all_ones_operand since it's not valid rtl. Add combine spiltter +;; for them, it should be safe since there's no SIMD Floating-Point Exceptions. +(define_insn_and_split "*bit_and_float_vector_all_ones" + [(set (match_operand:VFB 0 "nonimmediate_operand") + (and:VFB (match_operand:VFB 1 "nonimmediate_operand") + (match_operand:VFB 2 "float_vector_all_ones_operand")))] + "TARGET_SSE && ix86_pre_reload_split ()" + "#" + "&& 1" + [(set (match_dup 0) (match_dup 1))]) + (define_expand "copysign<mode>3" [(set (match_dup 4) (and:VFB |