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| author | Chao-ying Fu <fu@mips.com> | 2007-05-08 22:51:14 +0000 |
|---|---|---|
| committer | Chao-ying Fu <chaoyingfu@gcc.gnu.org> | 2007-05-08 22:51:14 +0000 |
| commit | 14661f36f8ef69c15d8a78a3c0ecbb03611df078 (patch) | |
| tree | 4f99bbafe98aff39b7f5885c910746129d4e95e8 /gcc/config | |
| parent | 10050f74a3151e7aa333bbbffb38dde95cb5e001 (diff) | |
| download | gcc-14661f36f8ef69c15d8a78a3c0ecbb03611df078.zip gcc-14661f36f8ef69c15d8a78a3c0ecbb03611df078.tar.gz gcc-14661f36f8ef69c15d8a78a3c0ecbb03611df078.tar.bz2 | |
md.texi (msub@var{m}@var{n}4, [...]): Document.
* doc/md.texi (msub@var{m}@var{n}4, usub@var{m}@var{n}4): Document.
* optabs.h (OTI_smsub_widen, OTI_umsub_widen): New optab_indexes.
(smsub_widen_optab, umsub_widen_optab): Define.
* optabs.c (init_optabs): Initialize smsub_widen_optab and
umsub_widen_optab.
* genopinit.c (optabs): Fill in smsub_widen_optab and
umsub_widen_optab.
* expr.c (expand_expr_real_1): Try to use smsub_widen_optab
and umsub_widen_optab to implement multiply-subtract sequences.
* config/mips/mips.md (*msac<u>_di): Rename to...
(<u>msubsidi4): ...this. Extend condition to include
GENERATE_MADD_MSUB and TARGET_DSPR2. Change the constraint
of operand 0 to "ka" and use the three-operand form of msub<u>
for TARGET_DSPR2.
* config/mips/mips-dspr2.md (mips_msub, mips_msubu): Convert
to define_expands.
From-SVN: r124558
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/mips/mips-dspr2.md | 30 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 10 |
2 files changed, 12 insertions, 28 deletions
diff --git a/gcc/config/mips/mips-dspr2.md b/gcc/config/mips/mips-dspr2.md index dd0aab5..2019008 100644 --- a/gcc/config/mips/mips-dspr2.md +++ b/gcc/config/mips/mips-dspr2.md @@ -162,31 +162,13 @@ (match_operand:DI 1 "register_operand")))] "TARGET_DSPR2 && !TARGET_64BIT") -(define_insn "mips_msub" - [(set (match_operand:DI 0 "register_operand" "=a") - (minus:DI - (match_operand:DI 1 "register_operand" "0") - (mult:DI (sign_extend:DI - (match_operand:SI 2 "register_operand" "d")) - (sign_extend:DI - (match_operand:SI 3 "register_operand" "d")))))] - "TARGET_DSPR2 && !TARGET_64BIT" - "msub\t%q0,%2,%3" - [(set_attr "type" "imadd") - (set_attr "mode" "SI")]) - -(define_insn "mips_msubu" - [(set (match_operand:DI 0 "register_operand" "=a") +(define_expand "mips_msub<u>" + [(set (match_operand:DI 0 "register_operand") (minus:DI - (match_operand:DI 1 "register_operand" "0") - (mult:DI (zero_extend:DI - (match_operand:SI 2 "register_operand" "d")) - (zero_extend:DI - (match_operand:SI 3 "register_operand" "d")))))] - "TARGET_DSPR2 && !TARGET_64BIT" - "msubu\t%q0,%2,%3" - [(set_attr "type" "imadd") - (set_attr "mode" "SI")]) + (match_operand:DI 1 "register_operand") + (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand")) + (any_extend:DI (match_operand:SI 3 "register_operand")))))] + "TARGET_DSPR2 && !TARGET_64BIT") (define_insn "mulv2hi3" [(parallel diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index e44b919..de592b9 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -1649,16 +1649,18 @@ [(set_attr "type" "imul") (set_attr "mode" "SI")]) -(define_insn "*msac<u>_di" - [(set (match_operand:DI 0 "register_operand" "=x") +(define_insn "<u>msubsidi4" + [(set (match_operand:DI 0 "register_operand" "=ka") (minus:DI (match_operand:DI 3 "register_operand" "0") (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))] - "!TARGET_64BIT && ISA_HAS_MSAC" + "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || TARGET_DSPR2)" { - if (TARGET_MIPS5500) + if (TARGET_DSPR2) + return "msub<u>\t%q0,%1,%2"; + else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB) return "msub<u>\t%1,%2"; else return "msac<u>\t$0,%1,%2"; |