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| author | Richard Earnshaw <rearnsha@arm.com> | 2019-10-18 19:03:19 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2019-10-18 19:03:19 +0000 |
| commit | 0b478cddf9e95406cd865c94bf99705ec8acddde (patch) | |
| tree | e4aea46ee82842c8dc421bca46b1c22e20ade936 /gcc/config | |
| parent | f6ff841bc8dd87ce364deb217dc6d1ec5dc31de8 (diff) | |
| download | gcc-0b478cddf9e95406cd865c94bf99705ec8acddde.zip gcc-0b478cddf9e95406cd865c94bf99705ec8acddde.tar.gz gcc-0b478cddf9e95406cd865c94bf99705ec8acddde.tar.bz2 | |
[arm] Add alternative canonicalizations for subtract-with-carry + shift
This patch adds a couple of alternative canonicalizations to allow
combine to match a subtract-with-carry operation when one of the operands
is shifted first. The most common case of this is when combining a
sign-extend of one operand with a long-long value during subtraction.
The RSC variant is only enabled for Arm, the SBC variant for any 32-bit
compilation.
* config/arm/arm.md (subsi3_carryin_shift_alt): New pattern.
(rsbsi3_carryin_shift_alt): Likewise.
From-SVN: r277176
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/arm/arm.md | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 74f417f..613f50a 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1048,6 +1048,23 @@ (const_string "alu_shift_reg")))] ) +(define_insn "*subsi3_carryin_shift_alt" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (minus:SI (minus:SI + (match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 5 "arm_borrow_operation" "")) + (match_operator:SI 2 "shift_operator" + [(match_operand:SI 3 "s_register_operand" "r") + (match_operand:SI 4 "reg_or_int_operand" "rM")])))] + "TARGET_32BIT" + "sbc%?\\t%0, %1, %3%S2" + [(set_attr "conds" "use") + (set_attr "predicable" "yes") + (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") + (const_string "alu_shift_imm") + (const_string "alu_shift_reg")))] +) + (define_insn "*rsbsi3_carryin_shift" [(set (match_operand:SI 0 "s_register_operand" "=r") (minus:SI (minus:SI @@ -1065,6 +1082,23 @@ (const_string "alu_shift_reg")))] ) +(define_insn "*rsbsi3_carryin_shift_alt" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (minus:SI (minus:SI + (match_operator:SI 2 "shift_operator" + [(match_operand:SI 3 "s_register_operand" "r") + (match_operand:SI 4 "reg_or_int_operand" "rM")]) + (match_operand:SI 5 "arm_borrow_operation" "")) + (match_operand:SI 1 "s_register_operand" "r")))] + "TARGET_ARM" + "rsc%?\\t%0, %1, %3%S2" + [(set_attr "conds" "use") + (set_attr "predicable" "yes") + (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") + (const_string "alu_shift_imm") + (const_string "alu_shift_reg")))] +) + ; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant. (define_split [(set (match_operand:SI 0 "s_register_operand" "") |