AVX10.2 ymm rounding: Support vfnmsub{132,231,213}p{s,d,h} intrins

gcc/ChangeLog:

	* config/i386/avx10_2roundingintrin.h: New intrins.
	* config/i386/i386-builtin.def (BDESC): Add new builtins.
	* config/i386/sse.md:
	(<avx512>_fnmsub_<mode>_mask3<round_name>): Add condition check.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx-1.c: Add new builtin test.
	* gcc.target/i386/sse-13.c: Ditto.
	* gcc.target/i386/sse-14.c: Ditto.
	* gcc.target/i386/sse-22.c: Add new macro test.
	* gcc.target/i386/sse-23.c: Ditto.
	* gcc.target/i386/avx10_2-rounding-3.c: Add test.

3 files changed, 191 insertions, 1 deletions

diff --git a/gcc/config/i386/avx10_2roundingintrin.h b/gcc/config/i386/avx10_2roundingintrin.h
index 3f833bf..afc1220 100644
--- a/gcc/config/i386/avx10_2roundingintrin.h
+++ b/gcc/config/i386/avx10_2roundingintrin.h
@@ -2876,6 +2876,151 @@ _mm256_maskz_fnmadd_round_ps (__mmask8 __U, __m256 __A, __m256 __B,
 							   (__mmask8) __U,
 							   __R);
 }
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_fnmsub_round_pd (__m256d __A, __m256d __B, __m256d __D, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfnmsubpd256_mask_round ((__v4df) __A,
+							   (__v4df) __B,
+							   (__v4df) __D,
+							   (__mmask8) -1,
+							   __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_fnmsub_round_pd (__m256d __A, __mmask8 __U, __m256d __B,
+			     __m256d __D, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfnmsubpd256_mask_round ((__v4df) __A,
+							   (__v4df) __B,
+							   (__v4df) __D,
+							   (__mmask8) __U,
+							   __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask3_fnmsub_round_pd (__m256d __A, __m256d __B, __m256d __D,
+			      __mmask8 __U, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfnmsubpd256_mask3_round ((__v4df) __A,
+							    (__v4df) __B,
+							    (__v4df) __D,
+							    (__mmask8) __U,
+							    __R);
+}
+
+extern __inline __m256d
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_fnmsub_round_pd (__mmask8 __U, __m256d __A, __m256d __B,
+			      __m256d __D, const int __R)
+{
+  return (__m256d) __builtin_ia32_vfnmsubpd256_maskz_round ((__v4df) __A,
+							    (__v4df) __B,
+							    (__v4df) __D,
+							    (__mmask8) __U,
+							    __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_fnmsub_round_ph (__m256h __A, __m256h __B, __m256h __D, const int __R)
+{
+  return (__m256h)
+    __builtin_ia32_vfnmsubph256_mask_round ((__v16hf) __A,
+					    (__v16hf) __B,
+					    (__v16hf) __D,
+					    (__mmask16) -1,
+					    __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_fnmsub_round_ph (__m256h __A, __mmask16 __U, __m256h __B,
+			     __m256h __D, const int __R)
+{
+  return (__m256h)
+    __builtin_ia32_vfnmsubph256_mask_round ((__v16hf) __A,
+					    (__v16hf) __B,
+					    (__v16hf) __D,
+					    (__mmask16) __U,
+					    __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask3_fnmsub_round_ph (__m256h __A, __m256h __B, __m256h __D,
+			      __mmask16 __U, const int __R)
+{
+  return (__m256h)
+    __builtin_ia32_vfnmsubph256_mask3_round ((__v16hf) __A,
+					     (__v16hf) __B,
+					     (__v16hf) __D,
+					     (__mmask16) __U,
+					     __R);
+}
+
+extern __inline __m256h
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_fnmsub_round_ph (__mmask16 __U, __m256h __A, __m256h __B,
+			      __m256h __D, const int __R)
+{
+  return (__m256h)
+    __builtin_ia32_vfnmsubph256_maskz_round ((__v16hf) __A,
+					     (__v16hf) __B,
+					     (__v16hf) __D,
+					     (__mmask16) __U,
+					     __R);
+}
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_fnmsub_round_ps (__m256 __A, __m256 __B, __m256 __D, const int __R)
+{
+  return (__m256) __builtin_ia32_vfnmsubps256_mask_round ((__v8sf) __A,
+							  (__v8sf) __B,
+							  (__v8sf) __D,
+							  (__mmask8) -1,
+							  __R);
+}
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_fnmsub_round_ps (__m256 __A, __mmask8 __U, __m256 __B,
+			     __m256 __D, const int __R)
+{
+  return (__m256) __builtin_ia32_vfnmsubps256_mask_round ((__v8sf) __A,
+							  (__v8sf) __B,
+							  (__v8sf) __D,
+							  (__mmask8) __U,
+							  __R);
+}
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask3_fnmsub_round_ps (__m256 __A, __m256 __B, __m256 __D,
+			      __mmask8 __U, const int __R)
+{
+  return (__m256) __builtin_ia32_vfnmsubps256_mask3_round ((__v8sf) __A,
+							   (__v8sf) __B,
+							   (__v8sf) __D,
+							   (__mmask8) __U,
+							   __R);
+}
+
+extern __inline __m256
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_fnmsub_round_ps (__mmask8 __U, __m256 __A, __m256 __B,
+			      __m256 __D, const int __R)
+{
+  return (__m256) __builtin_ia32_vfnmsubps256_maskz_round ((__v8sf) __A,
+							   (__v8sf) __B,
+							   (__v8sf) __D,
+							   (__mmask8) __U,
+							   __R);
+}
 #else
 #define _mm256_add_round_pd(A, B, R) \
   ((__m256d) __builtin_ia32_addpd256_mask_round ((__v4df) (A), \
@@ -4328,6 +4473,42 @@ _mm256_maskz_fnmadd_round_ps (__mmask8 __U, __m256 __A, __m256 __B,
 
 #define _mm256_maskz_fnmadd_round_ps(U, A, B, D, R)   \
   (__m256)__builtin_ia32_vfnmaddps256_maskz_round (A, B, D, U, R)
+
+#define _mm256_fnmsub_round_pd(A, B, D, R)	      \
+  (__m256d)__builtin_ia32_vfnmsubpd256_mask_round (A, B, D, -1, R)
+
+#define _mm256_mask_fnmsub_round_pd(A, U, B, D, R)    \
+  (__m256d)__builtin_ia32_vfnmsubpd256_mask_round (A, B, D, U, R)
+
+#define _mm256_mask3_fnmsub_round_pd(A, B, D, U, R)   \
+  (__m256d)__builtin_ia32_vfnmsubpd256_mask3_round (A, B, D, U, R)
+
+#define _mm256_maskz_fnmsub_round_pd(U, A, B, D, R)   \
+  (__m256d)__builtin_ia32_vfnmsubpd256_maskz_round (A, B, D, U, R)
+
+#define _mm256_fnmsub_round_ph(A, B, D, R)	    \
+  ((__m256h)__builtin_ia32_vfnmsubph256_mask_round ((A), (B), (D), -1, (R)))
+
+#define _mm256_mask_fnmsub_round_ph(A, U, B, D, R)	  \
+  ((__m256h)__builtin_ia32_vfnmsubph256_mask_round ((A), (B), (D), (U), (R)))
+
+#define _mm256_mask3_fnmsub_round_ph(A, B, D, U, R)	  \
+  ((__m256h)__builtin_ia32_vfnmsubph256_mask3_round ((A), (B), (D), (U), (R)))
+
+#define _mm256_maskz_fnmsub_round_ph(U, A, B, D, R)	  \
+  ((__m256h)__builtin_ia32_vfnmsubph256_maskz_round ((A), (B), (D), (U), (R)))
+
+#define _mm256_fnmsub_round_ps(A, B, D, R)	      \
+  (__m256)__builtin_ia32_vfnmsubps256_mask_round (A, B, D, -1, R)
+
+#define _mm256_mask_fnmsub_round_ps(A, U, B, D, R)    \
+  (__m256)__builtin_ia32_vfnmsubps256_mask_round (A, B, D, U, R)
+
+#define _mm256_mask3_fnmsub_round_ps(A, B, D, U, R)   \
+  (__m256)__builtin_ia32_vfnmsubps256_mask3_round (A, B, D, U, R)
+
+#define _mm256_maskz_fnmsub_round_ps(U, A, B, D, R)   \
+  (__m256)__builtin_ia32_vfnmsubps256_maskz_round (A, B, D, U, R)
 #endif
 
 #define _mm256_cmul_round_pch(A, B, R) _mm256_fcmul_round_pch ((A), (B), (R))
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 98a725b..74a8c60 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -3436,6 +3436,15 @@ BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmadd_v16hf_maskz_rou
 BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmadd_v8sf_mask_round, "__builtin_ia32_vfnmaddps256_mask_round", IX86_BUILTIN_VFNMADDPS256_MASK_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT)
 BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmadd_v8sf_mask3_round, "__builtin_ia32_vfnmaddps256_mask3_round", IX86_BUILTIN_VFNMADDPS512_MASK3_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT)
 BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmadd_v8sf_maskz_round, "__builtin_ia32_vfnmaddps256_maskz_round", IX86_BUILTIN_VFNMADDPS256_MASKZ_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmsub_v4df_mask_round, "__builtin_ia32_vfnmsubpd256_mask_round", IX86_BUILTIN_VFNMSUBPD256_MASK_ROUND, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmsub_v4df_mask3_round, "__builtin_ia32_vfnmsubpd256_mask3_round", IX86_BUILTIN_VFNMSUBPD256_MASK3_ROUND, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmsub_v4df_maskz_round, "__builtin_ia32_vfnmsubpd256_maskz_round", IX86_BUILTIN_VFNMSUBPD256_MASKZ_ROUND, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmsub_v16hf_mask_round, "__builtin_ia32_vfnmsubph256_mask_round", IX86_BUILTIN_VFNMSUBPH256_MASK_ROUND, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UHI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmsub_v16hf_mask3_round, "__builtin_ia32_vfnmsubph256_mask3_round", IX86_BUILTIN_VFNMSUBPH256_MASK3_ROUND, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UHI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmsub_v16hf_maskz_round, "__builtin_ia32_vfnmsubph256_maskz_round", IX86_BUILTIN_VFNMSUBPH256_MASKZ_ROUND, UNKNOWN, (int) V16HF_FTYPE_V16HF_V16HF_V16HF_UHI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmsub_v8sf_mask_round, "__builtin_ia32_vfnmsubps256_mask_round", IX86_BUILTIN_VFNMSUBPS256_MASK_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmsub_v8sf_mask3_round, "__builtin_ia32_vfnmsubps256_mask3_round", IX86_BUILTIN_VFNMSUBPS512_MASK3_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_fnmsub_v8sf_maskz_round, "__builtin_ia32_vfnmsubps256_maskz_round", IX86_BUILTIN_VFNMSUBPS256_MASKZ_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT)
 
 BDESC_END (ROUND_ARGS, MULTI_ARG)
 
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index dd13ed2..0881a43 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -6061,7 +6061,7 @@
 	      (match_operand:VFH_AVX512VL 3 "register_operand" "0")))
 	  (match_dup 3)
 	  (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
-  "TARGET_AVX512F"
+  "TARGET_AVX512F && <round_mode_condition>"
   "vfnmsub231<ssemodesuffix>\t{<round_op5>%2, %1, %0%{%4%}|%0%{%4%}, %1, %2<round_op5>}"
   [(set_attr "type" "ssemuladd")
    (set_attr "prefix" "evex")