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| author | Uros Bizjak <uros@gcc.gnu.org> | 2008-05-13 23:33:40 +0200 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2008-05-13 23:33:40 +0200 |
| commit | 08e64088dac74db3f526e2d764096968635efc1a (patch) | |
| tree | faf20623d7f26db32790483abc61907577122f6a /gcc/config | |
| parent | af7ae5d1075e9e7f2eddd0a7b113ebca3429b9e4 (diff) | |
| download | gcc-08e64088dac74db3f526e2d764096968635efc1a.zip gcc-08e64088dac74db3f526e2d764096968635efc1a.tar.gz gcc-08e64088dac74db3f526e2d764096968635efc1a.tar.bz2 | |
re PR target/36222 (x86 fails to optimize out __v4si -> __m128i move)
PR target/36222
* config/i386/i386.c (ix86_expand_vector_init_general): Rearrange op0
and op1 expansion before vector concat to have less live pseudos.
testsuite/ChangeLog:
PR target/36222
* gcc.target/i386/pr36222-1.c: New test.
From-SVN: r135275
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/i386.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 6d551e0..945cd1b 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -23887,14 +23887,14 @@ ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode, /* For V4SF and V4SI, we implement a concat of two V2 vectors. Recurse to load the two halves. */ - op0 = gen_reg_rtx (half_mode); - v = gen_rtvec (2, XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1)); - ix86_expand_vector_init (false, op0, gen_rtx_PARALLEL (half_mode, v)); - op1 = gen_reg_rtx (half_mode); v = gen_rtvec (2, XVECEXP (vals, 0, 2), XVECEXP (vals, 0, 3)); ix86_expand_vector_init (false, op1, gen_rtx_PARALLEL (half_mode, v)); + op0 = gen_reg_rtx (half_mode); + v = gen_rtvec (2, XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1)); + ix86_expand_vector_init (false, op0, gen_rtx_PARALLEL (half_mode, v)); + use_vec_concat = true; } break; @@ -23911,10 +23911,10 @@ ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode, if (use_vec_concat) { - if (!register_operand (op0, half_mode)) - op0 = force_reg (half_mode, op0); if (!register_operand (op1, half_mode)) op1 = force_reg (half_mode, op1); + if (!register_operand (op0, half_mode)) + op0 = force_reg (half_mode, op0); emit_insn (gen_rtx_SET (VOIDmode, target, gen_rtx_VEC_CONCAT (mode, op0, op1))); |