Fix double word typos.

From-SVN: r225726

31 files changed, 33 insertions, 33 deletions

diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index 4062c27..e4f5b00 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -73,7 +73,7 @@ enum aarch64_symbol_context
    SYMBOL_SMALL_TLSDESC
    SYMBOL_SMALL_GOTTPREL
    SYMBOL_TLSLE
-   Each of of these represents a thread-local symbol, and corresponds to the
+   Each of these represents a thread-local symbol, and corresponds to the
    thread local storage relocation operator for the symbol being referred to.
 
    SYMBOL_TINY_ABSOLUTE
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 37f42fa..020f63c 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -897,7 +897,7 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm,
 	   here before rtl expand.  Tree IVOPT will generate rtl pattern to
 	   decide rtx costs, in which case pic_offset_table_rtx is not
 	   initialized.  For that case no need to generate the first adrp
-	   instruction as the the final cost for global variable access is
+	   instruction as the final cost for global variable access is
 	   one instruction.  */
 	if (gp_rtx != NULL)
 	  {
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 1e343fa..db51ef8 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -144,7 +144,7 @@
 ;; Instruction types and attributes
 ;; -------------------------------------------------------------------
 
-; The "type" attribute is is included here from AArch32 backend to be able
+; The "type" attribute is included here from AArch32 backend to be able
 ; to share pipeline descriptions.
 (include "../arm/types.md")
 
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index be51c77..0be70a8 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -4553,7 +4553,7 @@
   "TARGET_32BIT"
   "#" ; "rsbs\\t%Q0, %1, #0\;sbc\\t%R0,%R0,%R0"
       ;; Don't care what register is input to sbc,
-      ;; since we just just need to propagate the carry.
+      ;; since we just need to propagate the carry.
   "&& reload_completed"
   [(parallel [(set (reg:CC CC_REGNUM)
                    (compare:CC (const_int 0) (match_dup 1)))
diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md
index b296c8b..3c1bfb0 100644
--- a/gcc/config/arm/arm1020e.md
+++ b/gcc/config/arm/arm1020e.md
@@ -58,7 +58,7 @@
 
 ;; ALU instructions require three cycles to execute, and use the ALU
 ;; pipeline in each of the three stages.  The results are available
-;; after the execute stage stage has finished.
+;; after the execute stage has finished.
 ;;
 ;; If the destination register is the PC, the pipelines are stalled
 ;; for several cycles.  That case is not modeled here.
diff --git a/gcc/config/arm/arm1026ejs.md b/gcc/config/arm/arm1026ejs.md
index a0221cb..54fbedd 100644
--- a/gcc/config/arm/arm1026ejs.md
+++ b/gcc/config/arm/arm1026ejs.md
@@ -58,7 +58,7 @@
 
 ;; ALU instructions require three cycles to execute, and use the ALU
 ;; pipeline in each of the three stages.  The results are available
-;; after the execute stage stage has finished.
+;; after the execute stage has finished.
 ;;
 ;; If the destination register is the PC, the pipelines are stalled
 ;; for several cycles.  That case is not modeled here.
diff --git a/gcc/config/arm/arm926ejs.md b/gcc/config/arm/arm926ejs.md
index 6449a32..27a8aba 100644
--- a/gcc/config/arm/arm926ejs.md
+++ b/gcc/config/arm/arm926ejs.md
@@ -50,7 +50,7 @@
 
 ;; ALU instructions require three cycles to execute, and use the ALU
 ;; pipeline in each of the three stages.  The results are available
-;; after the execute stage stage has finished.
+;; after the execute stage has finished.
 ;;
 ;; If the destination register is the PC, the pipelines are stalled
 ;; for several cycles.  That case is not modeled here.
diff --git a/gcc/config/arm/fa526.md b/gcc/config/arm/fa526.md
index 68c912b..34eb0d3 100644
--- a/gcc/config/arm/fa526.md
+++ b/gcc/config/arm/fa526.md
@@ -54,7 +54,7 @@
 
 ;; ALU instructions require two cycles to execute, and use the ALU
 ;; pipeline in each of the three stages.  The results are available
-;; after the execute stage stage has finished.
+;; after the execute stage has finished.
 ;;
 ;; If the destination register is the PC, the pipelines are stalled
 ;; for several cycles.  That case is not modeled here.
diff --git a/gcc/config/arm/fa606te.md b/gcc/config/arm/fa606te.md
index f0a2819..60662a7 100644
--- a/gcc/config/arm/fa606te.md
+++ b/gcc/config/arm/fa606te.md
@@ -54,7 +54,7 @@
 
 ;; ALU instructions require two cycles to execute, and use the ALU
 ;; pipeline in each of the three stages.  The results are available
-;; after the execute stage stage has finished.
+;; after the execute stage has finished.
 ;;
 ;; If the destination register is the PC, the pipelines are stalled
 ;; for several cycles.  That case is not modeled here.
diff --git a/gcc/config/arm/fa626te.md b/gcc/config/arm/fa626te.md
index 68f38ea..573e2c1 100644
--- a/gcc/config/arm/fa626te.md
+++ b/gcc/config/arm/fa626te.md
@@ -60,7 +60,7 @@
 
 ;; ALU instructions require two cycles to execute, and use the ALU
 ;; pipeline in each of the three stages.  The results are available
-;; after the execute stage stage has finished.
+;; after the execute stage has finished.
 ;;
 ;; If the destination register is the PC, the pipelines are stalled
 ;; for several cycles.  That case is not modeled here.
diff --git a/gcc/config/arm/fa726te.md b/gcc/config/arm/fa726te.md
index 9aabb1f..63459f2 100644
--- a/gcc/config/arm/fa726te.md
+++ b/gcc/config/arm/fa726te.md
@@ -70,7 +70,7 @@
 
 ;; ALU instructions require three cycles to execute, and use the ALU
 ;; pipeline in each of the three stages.  The results are available
-;; after the execute stage stage has finished.
+;; after the execute stage has finished.
 ;;
 ;; If the destination register is the PC, the pipelines are stalled
 ;; for several cycles.  That case is not modeled here.
diff --git a/gcc/config/arm/fmp626.md b/gcc/config/arm/fmp626.md
index 0200fc9..5d43bd10 100644
--- a/gcc/config/arm/fmp626.md
+++ b/gcc/config/arm/fmp626.md
@@ -55,7 +55,7 @@
 
 ;; ALU instructions require two cycles to execute, and use the ALU
 ;; pipeline in each of the three stages.  The results are available
-;; after the execute stage stage has finished.
+;; after the execute stage has finished.
 ;;
 ;; If the destination register is the PC, the pipelines are stalled
 ;; for several cycles.  That case is not modeled here.
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index 9160f15..b6effec 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -463,7 +463,7 @@ typedef struct GTY ((for_user)) machopic_indirection
   /* True iff this entry is for a stub (as opposed to a non-lazy
      pointer).  */
   bool stub_p;
-  /* True iff this stub or pointer pointer has been referenced.  */
+  /* True iff this stub or pointer has been referenced.  */
   bool used;
 } machopic_indirection;
 
diff --git a/gcc/config/epiphany/epiphany.c b/gcc/config/epiphany/epiphany.c
index f5aca81..593c9a1 100644
--- a/gcc/config/epiphany/epiphany.c
+++ b/gcc/config/epiphany/epiphany.c
@@ -572,7 +572,7 @@ sfunc_symbol (const char *name)
 }
 
 /* X and Y are two things to compare using CODE in IN_MODE.
-   Emit the compare insn, construct the the proper cc reg in the proper
+   Emit the compare insn, construct the proper cc reg in the proper
    mode, and return the rtx for the cc reg comparison in CMODE.  */
 
 rtx
diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index 10394f3..15de223 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -1191,7 +1191,7 @@ frv_stack_info (void)
 	}
     }
 
-  /* Set up the sizes of each each field in the frame body, making the sizes
+  /* Set up the sizes of each field in the frame body, making the sizes
      of each be divisible by the size of a dword if dword operations might
      be used, or the size of a word otherwise.  */
   alignment = (TARGET_DWORD? 2 * UNITS_PER_WORD : UNITS_PER_WORD);
diff --git a/gcc/config/ft32/ft32.c b/gcc/config/ft32/ft32.c
index 50c721b..f2e2677 100644
--- a/gcc/config/ft32/ft32.c
+++ b/gcc/config/ft32/ft32.c
@@ -782,7 +782,7 @@ ft32_is_mem_pm (rtx o)
 
 /* Define this to return an RTX representing the place where a
    function returns or receives a value of data type RET_TYPE, a tree
-   node node representing a data type.  */
+   node representing a data type.  */
 #undef TARGET_FUNCTION_VALUE
 #define TARGET_FUNCTION_VALUE ft32_function_value
 #undef TARGET_LIBCALL_VALUE
diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h
index 5b3576b..82a3e07 100644
--- a/gcc/config/gnu-user.h
+++ b/gcc/config/gnu-user.h
@@ -125,7 +125,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 
 /* Link -lasan early on the command line.  For -static-libasan, don't link
    it for -shared link, the executable should be compiled with -static-libasan
-   in that case, and for executable link link with --{,no-}whole-archive around
+   in that case, and for executable link with --{,no-}whole-archive around
    it to force everything into the executable.  And similarly for -ltsan
    and -llsan.  */
 #if defined(HAVE_LD_STATIC_DYNAMIC)
diff --git a/gcc/config/h8300/constraints.md b/gcc/config/h8300/constraints.md
index 9b509e7..94f850a 100644
--- a/gcc/config/h8300/constraints.md
+++ b/gcc/config/h8300/constraints.md
@@ -45,7 +45,7 @@
 ;;     before reload so that register allocator will pick the second
 ;;     alternative.
 
-;;   - we would like 'D' to be be NO_REGS when the frame pointer isn't
+;;   - we would like 'D' to be NO_REGS when the frame pointer isn't
 ;;     live, but we the frame pointer may turn out to be needed after
 ;;     we start reload, and then we may have already decided we don't
 ;;     have a choice, so we can't do that.  Forcing the register
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 6b5af11..493e686 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -5067,7 +5067,7 @@ ix86_valid_target_attribute_tree (tree args,
 
   /* If the changed options are different from the default, rerun
      ix86_option_override_internal, and then save the options away.
-     The string options are are attribute options, and will be undone
+     The string options are attribute options, and will be undone
      when we copy the save structure.  */
   if (opts->x_ix86_isa_flags != def->x_ix86_isa_flags
       || opts->x_target_flags != def->x_target_flags
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index bc98389..354532a 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -4164,7 +4164,7 @@
   [(set_attr "type" "fmov")
    (set_attr "mode" "<MODE>,XF")])
 
-;; %%% This seems bad bad news.
+;; %%% This seems like bad news.
 ;; This cannot output into an f-reg because there is no way to be sure
 ;; of truncating in that case.  Otherwise this is just like a simple move
 ;; insn.  So we pretend we can output to a reg in order to get better
diff --git a/gcc/config/iq2000/iq2000.md b/gcc/config/iq2000/iq2000.md
index d0eee18..e87cb68 100644
--- a/gcc/config/iq2000/iq2000.md
+++ b/gcc/config/iq2000/iq2000.md
@@ -133,7 +133,7 @@
 ;; instruction takes a 28-bit value, but that value is not an offset.
 ;; Instead, it's bitwise-ored with the high-order four bits of the
 ;; instruction in the delay slot, which means it cannot be used to
-;; cross a 256MB boundary.  We could fall back back on the jr,
+;; cross a 256MB boundary.  We could fall back on the jr
 ;; instruction which allows full access to the entire address space,
 ;; but we do not do so at present.
 
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 8fd7f2d..26c2ba8 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -3245,7 +3245,7 @@ mips_legitimize_tls_address (rtx loc)
 
   model = SYMBOL_REF_TLS_MODEL (loc);
   /* Only TARGET_ABICALLS code can have more than one module; other
-     code must be be static and should not use a GOT.  All TLS models
+     code must be static and should not use a GOT.  All TLS models
      reduce to local exec in this situation.  */
   if (!TARGET_ABICALLS)
     model = TLS_MODEL_LOCAL_EXEC;
diff --git a/gcc/config/mmix/mmix.md b/gcc/config/mmix/mmix.md
index 879369b..0b431e7 100644
--- a/gcc/config/mmix/mmix.md
+++ b/gcc/config/mmix/mmix.md
@@ -1131,7 +1131,7 @@ DIVU %1,%1,%2\;GET %0,:rR\;NEGU %2,0,%0\;CSNN %0,$255,%2")
 				     MMIX_INCOMING_RETURN_ADDRESS_REGNUM);
 
   /* We need the frame-pointer to be live or the equivalent
-     expression, so refer to in in the pattern.  We can't use a MEM
+     expression, so refer to it in the pattern.  We can't use a MEM
      (that may contain out-of-range offsets in the final expression)
      for fear that middle-end will legitimize it or replace the address
      using temporary registers (which are not revived at this point).  */
diff --git a/gcc/config/moxie/moxie.c b/gcc/config/moxie/moxie.c
index 7744c2d..97e0093 100644
--- a/gcc/config/moxie/moxie.c
+++ b/gcc/config/moxie/moxie.c
@@ -658,7 +658,7 @@ moxie_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED,
 
 /* Define this to return an RTX representing the place where a
    function returns or receives a value of data type RET_TYPE, a tree
-   node node representing a data type.  */
+   node representing a data type.  */
 #undef TARGET_FUNCTION_VALUE
 #define TARGET_FUNCTION_VALUE moxie_function_value
 #undef TARGET_LIBCALL_VALUE
diff --git a/gcc/config/nds32/nds32.md b/gcc/config/nds32/nds32.md
index 487127b..3dc1ce8 100644
--- a/gcc/config/nds32/nds32.md
+++ b/gcc/config/nds32/nds32.md
@@ -1894,7 +1894,7 @@ create_template:
 
 ;; Subroutine call instruction returning no value.
 ;;   operands[0]: It should be a mem RTX whose address is
-;;                the the address of the function.
+;;                the address of the function.
 ;;   operands[1]: It is the number of bytes of arguments pushed as a const_int.
 ;;   operands[2]: It is the number of registers used as operands.
 
diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index d7daabf..9fd036f 100644
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -572,7 +572,7 @@ extern rtx hppa_pic_save_rtx (void);
    The INCOMING field tracks whether this is an "incoming" or
    "outgoing" argument.
    
-   The INDIRECT field indicates whether this is is an indirect
+   The INDIRECT field indicates whether this is an indirect
    call or not.
    
    The NARGS_PROTOTYPE field indicates that an argument does not
diff --git a/gcc/config/rs6000/aix.h b/gcc/config/rs6000/aix.h
index a79d819..dbcfb95 100644
--- a/gcc/config/rs6000/aix.h
+++ b/gcc/config/rs6000/aix.h
@@ -79,7 +79,7 @@
 #if HAVE_AS_REF
 /* Issue assembly directives that create a reference to the given DWARF table
    identifier label from the current function section.  This is defined to
-   ensure we drag frame frame tables associated with needed function bodies in
+   ensure we drag frame tables associated with needed function bodies in
    a link with garbage collection activated.  */
 #define ASM_OUTPUT_DWARF_TABLE_REF rs6000_aix_asm_output_dwarf_table_ref
 #endif
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index f253689..1518457 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -666,7 +666,7 @@ extern int rs6000_vector_align[];
 #define TARGET_DF_SPE	(TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT	\
 			 && !TARGET_FPRS && TARGET_E500_DOUBLE)
 
-/* Whether SF/DF operations are supported by by the normal floating point unit
+/* Whether SF/DF operations are supported by the normal floating point unit
    (or the vector/scalar unit).  */
 #define TARGET_SF_FPR	(TARGET_HARD_FLOAT && TARGET_FPRS		\
 			 && TARGET_SINGLE_FLOAT)
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 8b287eb..19600bc 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -9023,7 +9023,7 @@ sh_round_reg (const CUMULATIVE_ARGS& cum, machine_mode mode)
     : cum.arg_count[(int) GET_SH_ARG_CLASS (mode)]);
 }
 
-/* Return true if arg of the specified mode should be be passed in a register
+/* Return true if arg of the specified mode should be passed in a register
    or false otherwise.  */
 static bool
 sh_pass_in_reg_p (const CUMULATIVE_ARGS& cum, machine_mode mode,
diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md
index 731828b..75322e1 100644
--- a/gcc/config/tilegx/tilegx.md
+++ b/gcc/config/tilegx/tilegx.md
@@ -904,7 +904,7 @@
 ;; Addresses
 ;;
 
-;; The next three patterns are used to to materialize a position
+;; The next three patterns are used to materialize a position
 ;; independent address by adding the difference of two labels to a base
 ;; label in the text segment, assuming that the difference fits in 32
 ;; signed bits.
@@ -964,7 +964,7 @@
   "%1 = . + 8\n\tlnk\t%0"
   [(set_attr "type" "Y1")])
 
-;; The next three patterns are used to to materialize a position
+;; The next three patterns are used to materialize a position
 ;; independent address by adding the difference of two labels to a
 ;; base label in the text segment, assuming that the difference fits
 ;; in 32 signed bits.
@@ -997,7 +997,7 @@
   "flag_pic"
   "add<x>\t%0, %r1, %r2")
 
-;; The next three patterns are used to to materialize a position
+;; The next three patterns are used to materialize a position
 ;; independent 64-bit address by adding the difference of two labels to
 ;; a base label in the text segment, without any limitation on the size
 ;; of the difference.
diff --git a/gcc/config/tilepro/gen-mul-tables.cc b/gcc/config/tilepro/gen-mul-tables.cc
index 107e9f2..758aa08 100644
--- a/gcc/config/tilepro/gen-mul-tables.cc
+++ b/gcc/config/tilepro/gen-mul-tables.cc
@@ -22,7 +22,7 @@
    efficiently.
 
    This program should be compiled by a c++ compiler.  If it's
-   compiled with with -DTILEPRO, it generates the multiply table for
+   compiled with -DTILEPRO, it generates the multiply table for
    TILEPro; otherwise it generates the multiply table for TILE-Gx.
    Running the program produces the table in stdout.