s390: arch15: Load indexed address

Add instructions lxa and llxa.

gcc/ChangeLog:

	* config/s390/s390.md (*lxa<LXAMODE>_index): Add.
	(*lxa<LXAMODE>_displacement_index): Add.
	(*lxa<LXAMODE>_index_base): Add.
	(*lxa<LXAMODE>_displacement_index_base): Add.
	(*lxab_displacement_index_base): Add.
	(*llxa<LXAMODE>_displacement_index): Add.
	(*llxa<LXAMODE>_index_base): Add.
	(*llxa<LXAMODE>_displacement_index_base): Add.
	(*llxab_displacement_index_base): Add.

gcc/testsuite/ChangeLog:

	* gcc.target/s390/llxa-1.c: New test.
	* gcc.target/s390/llxa-2.c: New test.
	* gcc.target/s390/llxa-3.c: New test.
	* gcc.target/s390/lxa-1.c: New test.
	* gcc.target/s390/lxa-2.c: New test.
	* gcc.target/s390/lxa-3.c: New test.
	* gcc.target/s390/lxa-4.c: New test.

1 files changed, 105 insertions, 0 deletions

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 6a660f1..6fed6bf 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -1963,6 +1963,111 @@
                               *,*,yes")
 ])
 
+; LOAD INDEXED ADDRESS
+; lxab, lxah, lxaf, lxag, lxaq
+
+(define_int_iterator LXAMODEITER [1 2 3 4])
+(define_int_attr lxamode [(1 "h") (2 "f") (3 "g") (4 "q")])
+
+; see testsuite/gcc.target/s390/lxa-1.c
+(define_insn "*lxa<lxamode>_index"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(ashift:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "a"))
+		   (const_int LXAMODEITER)))]
+  "TARGET_ARCH15 && TARGET_64BIT"
+  "lxa<lxamode>\t%0,0(%1,0)"
+  [(set_attr "op_type" "RXY")])
+
+; see testsuite/gcc.target/s390/lxa-2.c
+(define_insn "*lxa<lxamode>_displacement_index"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(ashift:DI (sign_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "a")
+					    (match_operand:SI 2 "const_int_operand")))
+		   (const_int LXAMODEITER)))]
+  "TARGET_ARCH15 && TARGET_64BIT && INTVAL (operands[2]) >= -0x80000 && INTVAL (operands[2]) <= 0x7FFFF"
+  "lxa<lxamode>\t%0,%2(%1,0)"
+  [(set_attr "op_type" "RXY")])
+
+; see testsuite/gcc.target/s390/lxa-3.c
+(define_insn "*lxa<lxamode>_index_base"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(plus:DI (ashift:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "a"))
+			    (const_int LXAMODEITER))
+		 (match_operand:DI 2 "register_operand" "a")))]
+  "TARGET_ARCH15 && TARGET_64BIT"
+  "lxa<lxamode>\t%0,0(%1,%2)"
+  [(set_attr "op_type" "RXY")])
+
+; see testsuite/gcc.target/s390/lxa-4.c
+(define_insn "*lxa<lxamode>_displacement_index_base"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(plus:DI (ashift:DI (sign_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "a")
+						     (match_operand:SI 2 "const_int_operand")))
+			    (const_int LXAMODEITER))
+		 (match_operand:DI 3 "register_operand" "a")))]
+  "TARGET_ARCH15 && TARGET_64BIT && INTVAL (operands[2]) >= -0x80000 && INTVAL (operands[2]) <= 0x7FFFF"
+  "lxa<lxamode>\t%0,%2(%1,%3)"
+  [(set_attr "op_type" "RXY")])
+
+(define_insn "*lxab_displacement_index_base"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(plus:DI (sign_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "a")
+					  (match_operand:SI 2 "const_int_operand")))
+		 (match_operand:DI 3 "register_operand" "a")))]
+  "TARGET_ARCH15 && TARGET_64BIT && INTVAL (operands[2]) >= -0x80000 && INTVAL (operands[2]) <= 0x7FFFF"
+  "lxab\t%0,%2(%1,%3)"
+  [(set_attr "op_type" "RXY")])
+
+; LOAD LOGICAL INDEXED ADDRESS
+; llxab, llxah, llxaf, llxag, llxaq
+
+(define_int_attr LLXAMASK [(1 "8589934590") (2 "17179869180") (3 "34359738360") (4 "68719476720")])
+
+; see testsuite/gcc.target/s390/llxa-1.c
+(define_insn "*llxa<lxamode>_displacement_index"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(and:DI (ashift:DI (subreg:DI (plus:SI (match_operand:SI 1 "register_operand" "a")
+					       (match_operand:SI 2 "const_int_operand"))
+				      0)
+			   (const_int LXAMODEITER))
+		(const_int <LLXAMASK>)))]
+  "TARGET_ARCH15 && TARGET_64BIT && INTVAL (operands[2]) >= -0x80000 && INTVAL (operands[2]) <= 0x7FFFF"
+  "llxa<lxamode>\t%0,%2(%1,0)"
+  [(set_attr "op_type" "RXY")])
+
+; see testsuite/gcc.target/s390/llxa-2.c
+(define_insn "*llxa<lxamode>_index_base"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(plus:DI (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "a")
+				    (const_int LXAMODEITER))
+			 (const_int <LLXAMASK>))
+		 (match_operand:DI 2 "register_operand" "a")))]
+  "TARGET_ARCH15 && TARGET_64BIT"
+  "llxa<lxamode>\t%0,0(%1,%2)"
+  [(set_attr "op_type" "RXY")])
+
+; see testsuite/gcc.target/s390/llxa-3.c
+(define_insn "*llxa<lxamode>_displacement_index_base"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(plus:DI (and:DI (ashift:DI (subreg:DI (plus:SI (match_operand:SI 1 "register_operand" "a")
+							(match_operand:SI 2 "const_int_operand"))
+					       0)
+				    (const_int LXAMODEITER))
+			 (const_int <LLXAMASK>))
+		 (match_operand:DI 3 "register_operand" "a")))]
+  "TARGET_ARCH15 && TARGET_64BIT && INTVAL (operands[2]) >= -0x80000 && INTVAL (operands[2]) <= 0x7FFFF"
+  "llxa<lxamode>\t%0,%2(%1,%3)"
+  [(set_attr "op_type" "RXY")])
+
+(define_insn "*llxab_displacement_index_base"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(plus:DI (zero_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "a")
+					  (match_operand:SI 2 "const_int_operand")))
+		 (match_operand:DI 3 "register_operand" "a")))]
+  "TARGET_ARCH15 && TARGET_64BIT && INTVAL (operands[2]) >= -0x80000 && INTVAL (operands[2]) <= 0x7FFFF"
+  "llxab\t%0,%2(%1,%3)"
+  [(set_attr "op_type" "RXY")])
+
 ; Splitters for loading TLS pointer from UNSPEC_GET_TP.
 ; UNSPEC_GET_TP is used instead of %a0:P, since the latter is a hard register,
 ; and those are not handled by Partial Redundancy Elimination (gcse.cc), which