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| author | Jie Mei <jie.mei@oss.cipunited.com> | 2023-06-19 16:29:57 +0800 |
|---|---|---|
| committer | YunQiang Su <yunqiang.su@cipunited.com> | 2023-07-03 11:38:20 +0800 |
| commit | e3ee4289840f45d5e0219dea20d2fbb97a9b8894 (patch) | |
| tree | d17c9b4cd4a615e0603e157d02d6a30d75ef3727 /gcc/config/mips/mips.h | |
| parent | 773110dea48baed989f2b92bf2e1689cc2d87b60 (diff) | |
| download | gcc-e3ee4289840f45d5e0219dea20d2fbb97a9b8894.zip gcc-e3ee4289840f45d5e0219dea20d2fbb97a9b8894.tar.gz gcc-e3ee4289840f45d5e0219dea20d2fbb97a9b8894.tar.bz2 | |
MIPS: Add CACHE instruction for mips16e2
This patch adds CACHE instruction from mips16e2
with corresponding tests.
gcc/ChangeLog:
* config/mips/mips.cc(mips_9bit_offset_address_p): Restrict the
address register to M16_REGS for MIPS16.
(BUILTIN_AVAIL_MIPS16E2): Defined a new macro.
(AVAIL_MIPS16E2_OR_NON_MIPS16): Same as above.
(AVAIL_NON_MIPS16 (cache..)): Update to
AVAIL_MIPS16E2_OR_NON_MIPS16.
* config/mips/mips.h (ISA_HAS_CACHE): Add clause for ISA_HAS_MIPS16E2.
* config/mips/mips.md (mips_cache): Mark as extended MIPS16.
gcc/testsuite/ChangeLog:
* gcc.target/mips/mips16e2-cache.c: New tests for mips16e2.
Diffstat (limited to 'gcc/config/mips/mips.h')
| -rw-r--r-- | gcc/config/mips/mips.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 05ccd20..0b6ea78 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1386,7 +1386,8 @@ struct mips_cpu_info { #define TARGET_CACHE_BUILTIN (mips_isa >= MIPS_ISA_MIPS3) /* The CACHE instruction is available. */ -#define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16) +#define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && (!TARGET_MIPS16 \ + || TARGET_MIPS16E2)) /* Tell collect what flags to pass to nm. */ #ifndef NM_FLAGS |