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| author | Jie Mei <jie.mei@oss.cipunited.com> | 2023-06-19 16:29:56 +0800 |
|---|---|---|
| committer | YunQiang Su <yunqiang.su@cipunited.com> | 2023-07-03 11:34:47 +0800 |
| commit | 773110dea48baed989f2b92bf2e1689cc2d87b60 (patch) | |
| tree | 83dc483deb8afaf748360e1636a8909fccd3b179 /gcc/config/mips/mips.h | |
| parent | 95c6fb6a841989c47213fedca689de1d50658ecf (diff) | |
| download | gcc-773110dea48baed989f2b92bf2e1689cc2d87b60.zip gcc-773110dea48baed989f2b92bf2e1689cc2d87b60.tar.gz gcc-773110dea48baed989f2b92bf2e1689cc2d87b60.tar.bz2 | |
MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2
The MIPS16e2 ASE has PREF, LL and SC instructions,
they use 9 bits immediate, like mips32r6.
The MIPS32 PRE-R6 uses 16 bits immediate.
gcc/ChangeLog:
* config/mips/mips.h(ISA_HAS_9BIT_DISPLACEMENT): Add clause
for ISA_HAS_MIPS16E2.
(ISA_HAS_SYNC): Same as above.
(ISA_HAS_LL_SC): Same as above.
Diffstat (limited to 'gcc/config/mips/mips.h')
| -rw-r--r-- | gcc/config/mips/mips.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index e09a6c6..05ccd20 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1248,7 +1248,8 @@ struct mips_cpu_info { && !TARGET_MIPS16) /* ISA has data prefetch, LL and SC with limited 9-bit displacement. */ -#define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6) +#define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6 \ + || ISA_HAS_MIPS16E2) /* ISA has data indexed prefetch instructions. This controls use of 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. @@ -1341,7 +1342,8 @@ struct mips_cpu_info { #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16) /* ISA includes sync. */ -#define ISA_HAS_SYNC ((mips_isa >= MIPS_ISA_MIPS2 || TARGET_MIPS3900) && !TARGET_MIPS16) +#define ISA_HAS_SYNC ((mips_isa >= MIPS_ISA_MIPS2 || TARGET_MIPS3900) \ + && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2)) #define GENERATE_SYNC \ (target_flags_explicit & MASK_LLSC \ ? TARGET_LLSC && !TARGET_MIPS16 \ @@ -1350,7 +1352,8 @@ struct mips_cpu_info { /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC instructions. */ -#define ISA_HAS_LL_SC (mips_isa >= MIPS_ISA_MIPS2 && !TARGET_MIPS5900 && !TARGET_MIPS16) +#define ISA_HAS_LL_SC (mips_isa >= MIPS_ISA_MIPS2 && !TARGET_MIPS5900 \ + && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2)) #define GENERATE_LL_SC \ (target_flags_explicit & MASK_LLSC \ ? TARGET_LLSC && !TARGET_MIPS16 \ |