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| author | Jie Mei <jie.mei@oss.cipunited.com> | 2023-06-19 16:29:50 +0800 |
|---|---|---|
| committer | YunQiang Su <yunqiang.su@cipunited.com> | 2023-07-03 11:34:45 +0800 |
| commit | 926f2d09d9c1ffb8286583175ee4bb605903fbce (patch) | |
| tree | 95956f97c9dd9773bcf346dbf9986186a977d2d2 /gcc/config/mips/mips.h | |
| parent | 1ebf37ece33bf48401afd332d55ef7bb6aedb4ab (diff) | |
| download | gcc-926f2d09d9c1ffb8286583175ee4bb605903fbce.zip gcc-926f2d09d9c1ffb8286583175ee4bb605903fbce.tar.gz gcc-926f2d09d9c1ffb8286583175ee4bb605903fbce.tar.bz2 | |
MIPS: Add basic support for mips16e2
The MIPS16e2 ASE is an enhancement to the MIPS16e ASE,
which includes all MIPS16e instructions, with some addition.
It defines new special instructions for increasing
code density (e.g. Extend, PC-relative instructions, etc.).
This patch adds basic support for mips16e2 used by the
following series of patches.
gcc/ChangeLog:
* config/mips/mips.cc(mips_file_start): Add mips16e2 info
for output file.
* config/mips/mips.h(__mips_mips16e2): Defined a new
predefine macro.
(ISA_HAS_MIPS16E2): Defined a new macro.
(ASM_SPEC): Pass mmips16e2 to the assembler.
* config/mips/mips.opt: Add -m(no-)mips16e2 option.
* config/mips/predicates.md: Add clause for TARGET_MIPS16E2.
* doc/invoke.texi: Add -m(no-)mips16e2 option..
gcc/testsuite/ChangeLog:
* gcc.target/mips/mips.exp(mips_option_groups): Add -mmips16e2
option.
(mips-dg-init): Handle the recognization of mips16e2 targets.
(mips-dg-options): Add dependencies for mips16e2.
Diffstat (limited to 'gcc/config/mips/mips.h')
| -rw-r--r-- | gcc/config/mips/mips.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 6daf6d3..c678167 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -475,6 +475,9 @@ struct mips_cpu_info { if (mips_base_compression_flags & MASK_MIPS16) \ builtin_define ("__mips16"); \ \ + if (TARGET_MIPS16E2) \ + builtin_define ("__mips_mips16e2"); \ + \ if (TARGET_MIPS3D) \ builtin_define ("__mips3d"); \ \ @@ -1291,6 +1294,10 @@ struct mips_cpu_info { /* The MSA ASE is available. */ #define ISA_HAS_MSA (TARGET_MSA && !TARGET_MIPS16) +/* The MIPS16e V2 instructions are available. */ +#define ISA_HAS_MIPS16E2 (TARGET_MIPS16 && TARGET_MIPS16E2 \ + && !TARGET_64BIT) + /* True if the result of a load is not available to the next instruction. A nop will then be needed between instructions like "lw $4,..." and "addiu $4,$4,1". */ @@ -1450,6 +1457,7 @@ struct mips_cpu_info { %{msym32} %{mno-sym32} \ %{mtune=*}" \ FP_ASM_SPEC "\ +%{mmips16e2} \ %(subtarget_asm_spec)" /* Extra switches sometimes passed to the linker. */ |