MIPS: Add basic support for mips16e2

The MIPS16e2 ASE is an enhancement to the MIPS16e ASE,
which includes all MIPS16e instructions, with some addition.
It defines new special instructions for increasing
code density (e.g. Extend, PC-relative instructions, etc.).

This patch adds basic support for mips16e2 used by the
following series of patches.

gcc/ChangeLog:

	* config/mips/mips.cc(mips_file_start): Add mips16e2 info
	for output file.
	* config/mips/mips.h(__mips_mips16e2): Defined a new
	predefine macro.
	(ISA_HAS_MIPS16E2): Defined a new macro.
	(ASM_SPEC): Pass mmips16e2 to the assembler.
	* config/mips/mips.opt: Add -m(no-)mips16e2 option.
	* config/mips/predicates.md: Add clause for TARGET_MIPS16E2.
	* doc/invoke.texi: Add -m(no-)mips16e2 option..

gcc/testsuite/ChangeLog:
	* gcc.target/mips/mips.exp(mips_option_groups): Add -mmips16e2
	option.
	(mips-dg-init): Handle the recognization of mips16e2 targets.
	(mips-dg-options): Add dependencies for mips16e2.

6 files changed, 32 insertions, 2 deletions

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 1b9880d..9ded0a3 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -10145,7 +10145,8 @@ mips_file_start (void)
     fputs ("\t.module\tmsa\n", asm_out_file);
   if (TARGET_XPA)
     fputs ("\t.module\txpa\n", asm_out_file);
-  /* FIXME: MIPS16E2 is not supported by GCC? gas does support it */
+  if (TARGET_MIPS16E2)
+    fputs ("\t.module\tmips16e2\n", asm_out_file);
   if (TARGET_CRC)
     fputs ("\t.module\tcrc\n", asm_out_file);
   if (TARGET_GINV)
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 6daf6d3..c678167 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -475,6 +475,9 @@ struct mips_cpu_info {
       if (mips_base_compression_flags & MASK_MIPS16)			\
 	builtin_define ("__mips16");					\
 									\
+      if (TARGET_MIPS16E2)						\
+	builtin_define ("__mips_mips16e2");				\
+									\
       if (TARGET_MIPS3D)						\
 	builtin_define ("__mips3d");					\
 									\
@@ -1291,6 +1294,10 @@ struct mips_cpu_info {
 /* The MSA ASE is available.  */
 #define ISA_HAS_MSA		(TARGET_MSA && !TARGET_MIPS16)
 
+/* The MIPS16e V2 instructions are available.  */
+#define ISA_HAS_MIPS16E2       (TARGET_MIPS16 && TARGET_MIPS16E2 \
+				&& !TARGET_64BIT)
+
 /* True if the result of a load is not available to the next instruction.
    A nop will then be needed between instructions like "lw $4,..."
    and "addiu $4,$4,1".  */
@@ -1450,6 +1457,7 @@ struct mips_cpu_info {
 %{msym32} %{mno-sym32} \
 %{mtune=*}" \
 FP_ASM_SPEC "\
+%{mmips16e2} \
 %(subtarget_asm_spec)"
 
 /* Extra switches sometimes passed to the linker.  */
diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
index 195f5be..4968ed0 100644
--- a/gcc/config/mips/mips.opt
+++ b/gcc/config/mips/mips.opt
@@ -380,6 +380,10 @@ msplit-addresses
 Target Mask(SPLIT_ADDRESSES)
 Optimize lui/addiu address loads.
 
+mmips16e2
+Target Var(TARGET_MIPS16E2) Init(0)
+Enable the MIPS16e V2 instructions.
+
 msym32
 Target Var(TARGET_SYM32)
 Assume all symbols have 32-bit values.
diff --git a/gcc/config/mips/predicates.md b/gcc/config/mips/predicates.md
index e34de29..87460a6 100644
--- a/gcc/config/mips/predicates.md
+++ b/gcc/config/mips/predicates.md
@@ -369,7 +369,7 @@
 {
   /* When generating mips16 code, TARGET_LEGITIMATE_CONSTANT_P rejects
      CONST_INTs that can't be loaded using simple insns.  */
-  if (TARGET_MIPS16)
+  if (TARGET_MIPS16 && !TARGET_MIPS16E2)
     return false;
 
   /* Don't handle multi-word moves this way; we don't want to introduce
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 26bcbe2..ed51ad5 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -26895,6 +26895,13 @@ MIPS16 code generation can also be controlled on a per-function basis
 by means of @code{mips16} and @code{nomips16} attributes.
 @xref{Function Attributes}, for more information.
 
+@opindex mmips16e2
+@opindex mno-mips16e2
+@item -mmips16e2
+@itemx -mno-mips16e2
+Use (do not use) the MIPS16e2 ASE.  This option modifies the behavior
+of the @option{-mips16} option such that it targets the MIPS16e2 ASE@.
+
 @opindex mflip-mips16
 @item -mflip-mips16
 Generate MIPS16 code on alternating functions.  This option is provided
diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp
index 15d5742..e79f685 100644
--- a/gcc/testsuite/gcc.target/mips/mips.exp
+++ b/gcc/testsuite/gcc.target/mips/mips.exp
@@ -301,6 +301,7 @@ foreach option {
     loongson-mmi
     loongson-ext
     loongson-ext2
+    mips16e2
 } {
     lappend mips_option_groups $option "-m(no-|)$option"
 }
@@ -821,6 +822,12 @@ proc mips-dg-init {} {
 	    "-mno-mips16",
 	    #endif
 
+	    #ifdef __mips_mips16e2
+	    "-mmips16e2",
+	    #else
+	    "-mno-mips16e2",
+	    #endif
+
 	    #ifdef __mips3d
 	    "-mips3d",
 	    #else
@@ -1038,6 +1045,7 @@ proc mips-dg-options { args } {
     # dependency diagram.
     mips_option_dependency options "-mips16" "-mno-micromips"
     mips_option_dependency options "-mmicromips" "-mno-mips16"
+    mips_option_dependency options "-mmicromips" "-mno-mips16e2"
     mips_option_dependency options "-mips3d" "-mpaired-single"
     mips_option_dependency options "-mips3d" "-mno-micromips"
     mips_option_dependency options "-mpaired-single" "-mfp64"
@@ -1417,6 +1425,7 @@ proc mips-dg-options { args } {
 		mips_make_test_option options "-mfp32"
 	    }
 	    mips_make_test_option options "-mno-dsp"
+	    mips_make_test_option options "-mno-mips16e2"
 	    mips_make_test_option options "-mno-synci"
 	    mips_make_test_option options "-mno-micromips"
 	    mips_make_test_option options "-mnan=legacy"
@@ -1449,6 +1458,7 @@ proc mips-dg-options { args } {
 
     # Handle dependencies between options on the right of the diagram.
     mips_option_dependency options "-mno-dsp" "-mno-dspr2"
+    mips_option_dependency options "-mno-mips16" "-mno-mips16e2"
     mips_option_dependency options "-mno-explicit-relocs" "-mgpopt"
     switch -- [mips_test_option options small-data] {
 	"" -