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| author | Chenghua Xu <paul.hua.gm@gmail.com> | 2018-11-07 08:58:05 +0000 |
|---|---|---|
| committer | Chenghua Xu <paulhua@gcc.gnu.org> | 2018-11-07 08:58:05 +0000 |
| commit | 8fa1acc7caa5ef5786965234bdb83f8f7bc1c850 (patch) | |
| tree | 5e58d4a84629e4ad895d8d1da575771c52c08739 /gcc/config/mips/mips.h | |
| parent | 659ce7cb2924c4dc9938c3f6f0b8705a21903bd9 (diff) | |
| download | gcc-8fa1acc7caa5ef5786965234bdb83f8f7bc1c850.zip gcc-8fa1acc7caa5ef5786965234bdb83f8f7bc1c850.tar.gz gcc-8fa1acc7caa5ef5786965234bdb83f8f7bc1c850.tar.bz2 | |
Add support for Loongson 2K1000 processor.
gcc/
* config/mips/gs264e.md: New.
* config/mips/mips-cpus.def: Define gs264e.
* config/mips/mips-tables.opt: Regenerate.
* config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for
gs264e.
(mips_issue_rate): Add support for gs264e.
(mips_multipass_dfa_lookahead): Likewise.
* config/mips/mips.h: Define TARGET_GS264E and TUNE_GS264E.
(MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs264e.
(MIPS_ASE_MSA_SPEC): New.
(BASE_DRIVER_SELF_SPECS): march=gs264e implies -mmsa.
(ISA_HAS_FUSED_MADD4): Enable for TARGET_GS264E.
(ISA_HAS_UNFUSED_MADD4): Exclude TARGET_GS264E.
* config/mips/mips.md: Include gs264e.md.
(processor): Add gs264e.
* config/mips/mips.opt (MSA): Use Mask instead of Var.
* doc/invoke.texi: Add gs264e to supported architectures.
From-SVN: r265867
Diffstat (limited to 'gcc/config/mips/mips.h')
| -rw-r--r-- | gcc/config/mips/mips.h | 23 |
1 files changed, 17 insertions, 6 deletions
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 193d399..0a92cf6 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -268,6 +268,7 @@ struct mips_cpu_info { #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) #define TARGET_GS464 (mips_arch == PROCESSOR_GS464) #define TARGET_GS464E (mips_arch == PROCESSOR_GS464E) +#define TARGET_GS264E (mips_arch == PROCESSOR_GS264E) #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) @@ -301,6 +302,7 @@ struct mips_cpu_info { || mips_tune == PROCESSOR_LOONGSON_2F) #define TUNE_GS464 (mips_tune == PROCESSOR_GS464) #define TUNE_GS464E (mips_tune == PROCESSOR_GS464E) +#define TUNE_GS264E (mips_tune == PROCESSOR_GS264E) #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) @@ -794,8 +796,8 @@ struct mips_cpu_info { %{march=mips32r6: -mips32r6} \ %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ |march=xlr: -mips64} \ - %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=octeon \ - |march=xlp: -mips64r2} \ + %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=gs264e \ + |march=octeon|march=xlp: -mips64r2} \ %{march=mips64r3: -mips64r3} \ %{march=mips64r5: -mips64r5} \ %{march=mips64r6|march=i6400|march=i6500|march=p6600: -mips64r6}}" @@ -898,7 +900,9 @@ struct mips_cpu_info { MIPS_ISA_NAN2008_SPEC, \ MIPS_ASE_DSP_SPEC, \ MIPS_ASE_LOONGSON_MMI_SPEC, \ - MIPS_ASE_LOONGSON_EXT_SPEC + MIPS_ASE_LOONGSON_EXT_SPEC, \ + MIPS_ASE_MSA_SPEC + #define MIPS_ASE_DSP_SPEC \ "%{!mno-dsp: \ @@ -913,7 +917,12 @@ struct mips_cpu_info { #define MIPS_ASE_LOONGSON_EXT_SPEC \ "%{!mno-loongson-ext: \ %{march=loongson3a|march=gs464: -mloongson-ext} \ - {march=gs464e: %{!mno-loongson-ext2: -mloongson-ext2 -mloongson-ext}}}" + %{march=gs464e|march=gs264e: %{!mno-loongson-ext2: \ + -mloongson-ext2 -mloongson-ext}}}" + +#define MIPS_ASE_MSA_SPEC \ + "%{!mno-msa: \ + %{march=gs264e: -mmsa}}" #define DRIVER_SELF_SPECS \ MIPS_ISA_LEVEL_SPEC, \ @@ -1103,7 +1112,8 @@ struct mips_cpu_info { #define ISA_HAS_FUSED_MADD4 (mips_madd4 \ && (TARGET_MIPS8000 \ || TARGET_GS464 \ - || TARGET_GS464E)) + || TARGET_GS464E \ + || TARGET_GS264E)) /* ISA has 4 operand unfused madd instructions of the form 'd = [+-] (a * b [+-] c)'. */ @@ -1111,7 +1121,8 @@ struct mips_cpu_info { && ISA_HAS_FP4 \ && !TARGET_MIPS8000 \ && !TARGET_GS464 \ - && !TARGET_GS464E) + && !TARGET_GS464E \ + && !TARGET_GS264E) /* ISA has 3 operand r6 fused madd instructions of the form 'c = c [+-] (a * b)'. */ |