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| author | Chenghua Xu <paul.hua.gm@gmail.com> | 2018-11-07 08:53:42 +0000 |
|---|---|---|
| committer | Chenghua Xu <paulhua@gcc.gnu.org> | 2018-11-07 08:53:42 +0000 |
| commit | 659ce7cb2924c4dc9938c3f6f0b8705a21903bd9 (patch) | |
| tree | 6ed1fc1447d4d681337545e20de06843ae81f1e8 /gcc/config/mips/mips.h | |
| parent | 2b94a36d5da43bbcc494f7d25f0c379069a85d9b (diff) | |
| download | gcc-659ce7cb2924c4dc9938c3f6f0b8705a21903bd9.zip gcc-659ce7cb2924c4dc9938c3f6f0b8705a21903bd9.tar.gz gcc-659ce7cb2924c4dc9938c3f6f0b8705a21903bd9.tar.bz2 | |
Add support for Loongson 3A2000/3A3000 processor.
gcc/
* config/mips/gs464e.md: New.
* config/mips/mips-cpus.def: Define gs464e.
* config/mips/mips-tables.opt: Regenerate.
* config/mips/mips.c (mips_rtx_cost_data): Add DEFAULT_COSTS for
gs464e.
(mips_issue_rate): Add support for gs464e.
(mips_multipass_dfa_lookahead): Likewise.
(mips_option_override): Enable MMI, EXT and EXT2 for gs464e.
* config/mips/mips.h: Define TARGET_GS464E and TUNE_GS464E.
(MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464e.
(ISA_HAS_FUSED_MADD4): Enable for TARGET_GS464E.
(ISA_HAS_UNFUSED_MADD4): Exclude TARGET_GS464E.
* config/mips/mips.md: Include gs464e.md.
(processor): Add gs464e.
* doc/invoke.texi: Add gs464e to supported architectures.
From-SVN: r265866
Diffstat (limited to 'gcc/config/mips/mips.h')
| -rw-r--r-- | gcc/config/mips/mips.h | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 9666107..193d399 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -267,6 +267,7 @@ struct mips_cpu_info { #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F) #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) #define TARGET_GS464 (mips_arch == PROCESSOR_GS464) +#define TARGET_GS464E (mips_arch == PROCESSOR_GS464E) #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) @@ -299,6 +300,7 @@ struct mips_cpu_info { #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \ || mips_tune == PROCESSOR_LOONGSON_2F) #define TUNE_GS464 (mips_tune == PROCESSOR_GS464) +#define TUNE_GS464E (mips_tune == PROCESSOR_GS464E) #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) @@ -792,7 +794,7 @@ struct mips_cpu_info { %{march=mips32r6: -mips32r6} \ %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ |march=xlr: -mips64} \ - %{march=mips64r2|march=loongson3a|march=gs464|march=octeon \ + %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=octeon \ |march=xlp: -mips64r2} \ %{march=mips64r3: -mips64r3} \ %{march=mips64r5: -mips64r5} \ @@ -910,7 +912,8 @@ struct mips_cpu_info { #define MIPS_ASE_LOONGSON_EXT_SPEC \ "%{!mno-loongson-ext: \ - %{march=loongson3a|march=gs464: -mloongson-ext}}" + %{march=loongson3a|march=gs464: -mloongson-ext} \ + {march=gs464e: %{!mno-loongson-ext2: -mloongson-ext2 -mloongson-ext}}}" #define DRIVER_SELF_SPECS \ MIPS_ISA_LEVEL_SPEC, \ @@ -1099,14 +1102,16 @@ struct mips_cpu_info { 'd = [+-] (a * b [+-] c)'. */ #define ISA_HAS_FUSED_MADD4 (mips_madd4 \ && (TARGET_MIPS8000 \ - || TARGET_GS464)) + || TARGET_GS464 \ + || TARGET_GS464E)) /* ISA has 4 operand unfused madd instructions of the form 'd = [+-] (a * b [+-] c)'. */ #define ISA_HAS_UNFUSED_MADD4 (mips_madd4 \ && ISA_HAS_FP4 \ && !TARGET_MIPS8000 \ - && !TARGET_GS464) + && !TARGET_GS464 \ + && !TARGET_GS464E) /* ISA has 3 operand r6 fused madd instructions of the form 'c = c [+-] (a * b)'. */ |