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| author | Jie Mei <jie.mei@oss.cipunited.com> | 2023-06-19 16:29:55 +0800 |
|---|---|---|
| committer | YunQiang Su <yunqiang.su@cipunited.com> | 2023-07-03 11:34:46 +0800 |
| commit | 95c6fb6a841989c47213fedca689de1d50658ecf (patch) | |
| tree | 34ca2aad2813306d329bf8342db8d032799e65ca /gcc/config/mips/mips.h | |
| parent | eeedb137120079cc8d349286f234b06efb71fa48 (diff) | |
| download | gcc-95c6fb6a841989c47213fedca689de1d50658ecf.zip gcc-95c6fb6a841989c47213fedca689de1d50658ecf.tar.gz gcc-95c6fb6a841989c47213fedca689de1d50658ecf.tar.bz2 | |
MIPS: Add load/store word left/right instructions for mips16e2
This patch adds LWL/LWR, SWL/SWR instructions with their
corresponding tests.
gcc/ChangeLog:
* config/mips/mips.cc(mips_expand_ins_as_unaligned_store):
Add logics for generating instruction.
* config/mips/mips.h(ISA_HAS_LWL_LWR): Add clause for ISA_HAS_MIPS16E2.
* config/mips/mips.md(mov_<load>l): Generates instructions.
(mov_<load>r): Same as above.
(mov_<store>l): Adjusted for the conditions above.
(mov_<store>r): Same as above.
(mov_<store>l_mips16e2): Add machine description for `define_insn mov_<store>l_mips16e2`.
(mov_<store>r_mips16e2): Add machine description for `define_insn mov_<store>r_mips16e2`.
gcc/testsuite/ChangeLog:
* gcc.target/mips/mips16e2.c: New tests for mips16e2.
Diffstat (limited to 'gcc/config/mips/mips.h')
| -rw-r--r-- | gcc/config/mips/mips.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index eefe2aa..e09a6c6 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1180,7 +1180,8 @@ struct mips_cpu_info { && (MODE) == V2SFmode)) \ && !TARGET_MIPS16) -#define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 && !TARGET_MIPS16) +#define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 \ + && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2)) #define ISA_HAS_IEEE_754_LEGACY (mips_isa_rev <= 5) |