diff options
| author | Jie Mei <jie.mei@oss.cipunited.com> | 2023-06-19 16:29:52 +0800 |
|---|---|---|
| committer | YunQiang Su <yunqiang.su@cipunited.com> | 2023-07-03 11:34:46 +0800 |
| commit | 26aa2a2ccecf125af8eb9977b7638c7ca2d053e8 (patch) | |
| tree | 22f653933abdc520258ae01bcf1feea11e0b4902 /gcc/config/mips/mips.h | |
| parent | d102aa2d30c6dc3bd88170dedd16b07e7b7709e6 (diff) | |
| download | gcc-26aa2a2ccecf125af8eb9977b7638c7ca2d053e8.zip gcc-26aa2a2ccecf125af8eb9977b7638c7ca2d053e8.tar.gz gcc-26aa2a2ccecf125af8eb9977b7638c7ca2d053e8.tar.bz2 | |
MIPS: Add instruction about global pointer register for mips16e2
The mips16e2 ASE uses eight general-purpose registers
from mips32, with some special-purpose registers,
these registers are GPRs: s0-1, v0-1, a0-3, and
special registers: t8, gp, sp, ra.
As mentioned above, the special register gp is
used in mips16e2, which is the global pointer register,
it is used by some of the instructions in the ASE,
for instance, ADDIU, LB/LBU, etc. .
This patch adds these instructions with corresponding tests.
gcc/ChangeLog:
* config/mips/mips.cc(mips_regno_mode_ok_for_base_p): Generate instructions
that uses global pointer register.
(mips16_unextended_reference_p): Same as above.
(mips_pic_base_register): Same as above.
(mips_init_relocs): Same as above.
* config/mips/mips.h(MIPS16_GP_LOADS): Defined a new macro.
(GLOBAL_POINTER_REGNUM): Moved to machine description `mips.md`.
* config/mips/mips.md(GLOBAL_POINTER_REGNUM): Moved to here from above.
(*lowsi_mips16_gp):New `define_insn *low<mode>_mips16`.
gcc/testsuite/ChangeLog:
* gcc.target/mips/mips16e2-gp.c: New tests for mips16e2.
Diffstat (limited to 'gcc/config/mips/mips.h')
| -rw-r--r-- | gcc/config/mips/mips.h | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index a94b253..3ec33fb 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1375,6 +1375,8 @@ struct mips_cpu_info { /* ISA includes the pop instruction. */ #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16) +#define MIPS16_GP_LOADS (ISA_HAS_MIPS16E2 && !TARGET_64BIT) + /* The CACHE instruction is available in non-MIPS16 code. */ #define TARGET_CACHE_BUILTIN (mips_isa >= MIPS_ISA_MIPS3) @@ -2067,10 +2069,6 @@ FP_ASM_SPEC "\ function address than to call an address kept in a register. */ #define NO_FUNCTION_CSE 1 -/* The ABI-defined global pointer. Sometimes we use a different - register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */ -#define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28) - /* We normally use $28 as the global pointer. However, when generating n32/64 PIC, it is better for leaf functions to use a call-clobbered register instead. They can then avoid saving and restoring $28 |