Drop original H8/300 support. This should generate identical code for the remaining subtargets. Defaults to H8/300H codegen

	* config/h8300/constraints.md (L and N): Simplify now that we're not
	longer supporting the original H8/300 chip.
	* config/h8300/elf.h (LINK_SPEC): Likewise.  Default to H8/300H.
	* config/h8300/h8300.c (shift_alg_qi): Drop H8/300 support.
	(shift_alg_hi, shift_alg_si): Similarly.
	(h8300_option_overrides): Similarly.  Default to H8/300H.  If
	compiling for H8/S, then turn off H8/300H.  Do not update the
	shift_alg tables for H8/300 port.
	(h8300_emit_stack_adjustment): Remove support for H8/300.  Simplify
	where possible.
	(push, split_adds_subs, h8300_rtx_costs): Likewise.
	(h8300_print_operand, compute_mov_length): Likewise.
	(output_plussi, compute_plussi_length): Likewise.
	(compute_plussi_cc, output_logical_op): Likewise.
	(compute_logical_op_length, compute_logical_op_cc): Likewise.
	(get_shift_alg, h8300_shift_needs_scratch): Likewise.
	(output_a_shift, compute_a_shift_length): Likewise.
	(output_a_rotate, compute_a_rotate_length): Likewise.
	(output_simode_bld, h8300_hard_regno_mode_ok): Likewise.
	(h8300_modes_tieable_p, h8300_return_in_memory): Likewise.
	* config/h8300/h8300.h (TARGET_CPU_CPP_BUILTINS): Likewise.
	(attr_cpu, TARGET_H8300): Remove.
	(TARGET_DEFAULT): Update.
	(UNITS_PER_WORD, PARM_BOUNDARY): Simplify where possible.
	(BIGGEST_ALIGNMENT, STACK_BOUNDARY): Likewise.
	(CONSTANT_ADDRESS_P, MOVE_MAX, Pmode): Likewise.
	(SIZE_TYPE, POINTER_SIZE, ASM_WORD_OP): Likewise.
	* config/h8300/h8300.md: Simplify patterns throughout.
	* config/h8300/t-h8300: Update multilib configuration.

@@ -82,11 +82,9 @@

7 files changed, 653 insertions, 1639 deletions

diff --git a/gcc/config/h8300/constraints.md b/gcc/config/h8300/constraints.md
index fee44e8..d245182 100644
--- a/gcc/config/h8300/constraints.md
+++ b/gcc/config/h8300/constraints.md
@@ -82,11 +82,9 @@
        (match_test "(ival & 0xff) == 0")))
 
 (define_constraint "L"
-  "1, 2 or 4 on the H8300H or S; 1 or 2 otherwise."
+  "Integer 1, 2 or 4"
   (and (match_code "const_int")
-       (if_then_else (match_test "TARGET_H8300H || TARGET_H8300S")
-		     (match_test "ival == 1 || ival == 2 || ival == 4")
-		     (match_test "ival == 1 || ival == 2"))))
+       (match_test "ival == 1 || ival == 2 || ival == 4")))
 
 (define_constraint "M"
   "Integer 1 or 2."
@@ -94,11 +92,9 @@
        (match_test "ival == 1 || ival == 2")))
 
 (define_constraint "N"
-  "-1, -2, or -4 on the H8300H or S; -1 or -2 otherwise."
+  "Integer -1, -2 or -4"
   (and (match_code "const_int")
-       (if_then_else (match_test "TARGET_H8300H || TARGET_H8300S")
-		     (match_test "ival == -1 || ival == -2 || ival == -4")
-		     (match_test "ival == -1 || ival == -2"))))
+       (match_test "ival == -1 || ival == -2 || ival == -4")))
 
 (define_constraint "O"
   "Integer -1 or -2."
diff --git a/gcc/config/h8300/elf.h b/gcc/config/h8300/elf.h
index ca32673..06844a5 100644
--- a/gcc/config/h8300/elf.h
+++ b/gcc/config/h8300/elf.h
@@ -39,6 +39,6 @@ along with GCC; see the file COPYING3.  If not see
 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
 
 #undef LINK_SPEC
-#define LINK_SPEC "%{mh:%{mn:-m h8300hnelf}} %{mh:%{!mn:-m h8300helf}} %{ms:%{mn:-m h8300snelf}} %{ms:%{!mn:-m h8300self}} %{msx:%{mn:-m h8300sxnelf;:-m h8300sxelf}}"
+#define LINK_SPEC "%{!ms:%{!msx:%{mn:-m h8300hnelf;:-m h8300helf}}} %{ms:%{mn:-m h8300snelf;:-m h8300self}} %{msx:%{mn:-m h8300sxnelf;:-m h8300sxelf}}"
 
 #endif /* h8300/elf.h */
diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index 2c51c7c..6875cd9 100644
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -179,14 +179,7 @@ enum shift_type
    QImode, HImode, and SImode, respectively.  Each table is organized
    by, in the order of indices, machine, shift type, and shift count.  */
 
-static enum shift_alg shift_alg_qi[3][3][8] = {
-  {
-    /* TARGET_H8300  */
-    /* 0    1    2    3    4    5    6    7  */
-    { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT   */
-    { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */
-    { INL, INL, INL, INL, INL, LOP, LOP, SPC }  /* SHIFT_ASHIFTRT */
-  },
+static enum shift_alg shift_alg_qi[2][3][8] = {
   {
     /* TARGET_H8300H  */
     /* 0    1    2    3    4    5    6    7  */
@@ -203,18 +196,7 @@ static enum shift_alg shift_alg_qi[3][3][8] = {
   }
 };
 
-static enum shift_alg shift_alg_hi[3][3][16] = {
-  {
-    /* TARGET_H8300  */
-    /*  0    1    2    3    4    5    6    7  */
-    /*  8    9   10   11   12   13   14   15  */
-    { INL, INL, INL, INL, INL, INL, INL, SPC,
-      SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT   */
-    { INL, INL, INL, INL, INL, LOP, LOP, SPC,
-      SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */
-    { INL, INL, INL, INL, INL, LOP, LOP, SPC,
-      SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */
-  },
+static enum shift_alg shift_alg_hi[2][3][16] = {
   {
     /* TARGET_H8300H  */
     /*  0    1    2    3    4    5    6    7  */
@@ -239,26 +221,7 @@ static enum shift_alg shift_alg_hi[3][3][16] = {
   }
 };
 
-static enum shift_alg shift_alg_si[3][3][32] = {
-  {
-    /* TARGET_H8300  */
-    /*  0    1    2    3    4    5    6    7  */
-    /*  8    9   10   11   12   13   14   15  */
-    /* 16   17   18   19   20   21   22   23  */
-    /* 24   25   26   27   28   29   30   31  */
-    { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
-      SPC, LOP, LOP, LOP, LOP, LOP, LOP, LOP,
-      SPC, SPC, SPC, SPC, SPC, LOP, LOP, LOP,
-      SPC, SPC, SPC, SPC, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFT   */
-    { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
-      SPC, SPC, LOP, LOP, LOP, LOP, LOP, SPC,
-      SPC, SPC, SPC, LOP, LOP, LOP, LOP, LOP,
-      SPC, SPC, SPC, SPC, SPC, LOP, LOP, SPC }, /* SHIFT_LSHIFTRT */
-    { INL, INL, INL, LOP, LOP, LOP, LOP, LOP,
-      SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC,
-      SPC, SPC, LOP, LOP, LOP, LOP, LOP, LOP,
-      SPC, SPC, SPC, LOP, LOP, LOP, LOP, SPC }, /* SHIFT_ASHIFTRT */
-  },
+static enum shift_alg shift_alg_si[2][3][32] = {
   {
     /* TARGET_H8300H  */
     /*  0    1    2    3    4    5    6    7  */
@@ -306,7 +269,6 @@ static enum shift_alg shift_alg_si[3][3][32] = {
 
 enum h8_cpu
 {
-  H8_300,
   H8_300H,
   H8_S
 };
@@ -320,45 +282,29 @@ h8300_option_override (void)
   static const char *const h8_pop_ops[2]  = { "pop"  , "pop.l"  };
   static const char *const h8_mov_ops[2]  = { "mov.w", "mov.l"  };
 
-  if (TARGET_H8300)
-    {
-      cpu_type = (int) CPU_H8300;
-      h8_reg_names = names_big;
-    }
-  else
-    {
-      /* For this we treat the H8/300H and H8S the same.  */
-      cpu_type = (int) CPU_H8300H;
-      h8_reg_names = names_extended;
-    }
+  /* For this we treat the H8/300H and H8S the same.  */
+  cpu_type = (int) CPU_H8300H;
+  h8_reg_names = names_extended;
   h8_push_op = h8_push_ops[cpu_type];
   h8_pop_op = h8_pop_ops[cpu_type];
   h8_mov_op = h8_mov_ops[cpu_type];
 
+  /* If we're compiling for the H8/S, then turn off H8/300H.  */
+  if (TARGET_H8300S)
+    target_flags &= ~MASK_H8300H;
+
   if (!TARGET_H8300S && TARGET_MAC)
     {
       error ("%<-ms2600%> is used without %<-ms%>");
       target_flags |= MASK_H8300S_1;
     }
 
-  if (TARGET_H8300 && TARGET_NORMAL_MODE)
-    {
-      error ("%<-mn%> is used without %<-mh%> or %<-ms%> or %<-msx%>");
-      target_flags ^= MASK_NORMAL_MODE;
-    }
-
   if (! TARGET_H8300S &&  TARGET_EXR)
     {
       error ("%<-mexr%> is used without %<-ms%>");
       target_flags |= MASK_H8300S_1;
     }
 
-  if (TARGET_H8300 && TARGET_INT32)
-   {
-      error ("%<-mint32%> is not supported for H8300 and H8300L targets");
-      target_flags ^= MASK_INT32;
-   }
-
  if ((!TARGET_H8300S  &&  TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR))
    {
       error ("%<-mexr%> is used without %<-ms%> or %<-msx%>");
@@ -385,18 +331,6 @@ h8300_option_override (void)
      SHIFT_LOOP.  */
   if (optimize_size)
     {
-      /* H8/300 */
-      shift_alg_hi[H8_300][SHIFT_ASHIFT][5] = SHIFT_LOOP;
-      shift_alg_hi[H8_300][SHIFT_ASHIFT][6] = SHIFT_LOOP;
-      shift_alg_hi[H8_300][SHIFT_ASHIFT][13] = SHIFT_LOOP;
-      shift_alg_hi[H8_300][SHIFT_ASHIFT][14] = SHIFT_LOOP;
-
-      shift_alg_hi[H8_300][SHIFT_LSHIFTRT][13] = SHIFT_LOOP;
-      shift_alg_hi[H8_300][SHIFT_LSHIFTRT][14] = SHIFT_LOOP;
-
-      shift_alg_hi[H8_300][SHIFT_ASHIFTRT][13] = SHIFT_LOOP;
-      shift_alg_hi[H8_300][SHIFT_ASHIFTRT][14] = SHIFT_LOOP;
-
       /* H8/300H */
       shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP;
       shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP;
@@ -524,38 +458,22 @@ h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size, bool in_prologue)
   if (size == 0)
     return;
 
-  /* H8/300 cannot add/subtract a large constant with a single
-     instruction.  If a temporary register is available, load the
-     constant to it and then do the addition.  */
-  if (TARGET_H8300
-      && size > 4
-      && !h8300_current_function_interrupt_function_p ()
-      && !(cfun->static_chain_decl != NULL && sign < 0))
+  /* The stack adjustment made here is further optimized by the
+     splitter.  In case of H8/300, the splitter always splits the
+     addition emitted here to make the adjustment interrupt-safe.
+     FIXME: We don't always tag those, because we don't know what
+     the splitter will do.  */
+  if (Pmode == HImode)
     {
-      rtx r3 = gen_rtx_REG (Pmode, 3);
-      F (emit_insn (gen_movhi (r3, GEN_INT (sign * size))), in_prologue);
-      F (emit_insn (gen_addhi3 (stack_pointer_rtx,
-				stack_pointer_rtx, r3)), in_prologue);
+      rtx_insn *x = emit_insn (gen_addhi3 (stack_pointer_rtx,
+					   stack_pointer_rtx,
+					    GEN_INT (sign * size)));
+      if (size < 4)
+        F (x, in_prologue);
     }
   else
-    {
-      /* The stack adjustment made here is further optimized by the
-	 splitter.  In case of H8/300, the splitter always splits the
-	 addition emitted here to make the adjustment interrupt-safe.
-	 FIXME: We don't always tag those, because we don't know what
-	 the splitter will do.  */
-      if (Pmode == HImode)
-	{
-	  rtx_insn *x = emit_insn (gen_addhi3 (stack_pointer_rtx,
-					       stack_pointer_rtx,
-					       GEN_INT (sign * size)));
-	  if (size < 4)
-	    F (x, in_prologue);
-	}
-      else
-	F (emit_insn (gen_addsi3 (stack_pointer_rtx,
-				  stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
-    }
+    F (emit_insn (gen_addsi3 (stack_pointer_rtx,
+			      stack_pointer_rtx, GEN_INT (sign * size))), in_prologue);
 }
 
 /* Round up frame size SIZE.  */
@@ -598,9 +516,7 @@ push (int rn, bool in_prologue)
   rtx reg = gen_rtx_REG (word_mode, rn);
   rtx x;
 
-  if (TARGET_H8300)
-    x = gen_push_h8300 (reg);
-  else if (!TARGET_NORMAL_MODE)
+  if (!TARGET_NORMAL_MODE)
     x = gen_push_h8300hs_advanced (reg);
   else
     x = gen_push_h8300hs_normal (reg);
@@ -617,9 +533,7 @@ pop (int rn)
   rtx reg = gen_rtx_REG (word_mode, rn);
   rtx x;
 
-  if (TARGET_H8300)
-    x = gen_pop_h8300 (reg);
-  else if (!TARGET_NORMAL_MODE)
+  if (!TARGET_NORMAL_MODE)
     x = gen_pop_h8300hs_advanced (reg);
   else
     x = gen_pop_h8300hs_normal (reg);
@@ -1038,9 +952,7 @@ split_adds_subs (machine_mode mode, rtx *operands)
     }
 
   /* Try different amounts in descending order.  */
-  for (amount = (TARGET_H8300H || TARGET_H8300S) ? 4 : 2;
-       amount > 0;
-       amount /= 2)
+  for (amount = 4; amount > 0; amount /= 2)
     {
       for (; val >= amount; val -= amount)
 	emit_insn (gen_add (reg, reg, GEN_INT (sign * amount)));
@@ -1262,10 +1174,7 @@ h8300_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code,
 		return true;
 	      case 4:
 	      case -4:
-		if (TARGET_H8300H || TARGET_H8300S)
-		  *total = 0 + (outer_code == SET);
-		else
-		  *total = 1;
+		*total = 0 + (outer_code == SET);
 		return true;
 	      }
 	  }
@@ -1554,10 +1463,7 @@ h8300_print_operand (FILE *file, rtx x, int code)
       switch (GET_CODE (x))
 	{
 	case REG:
-	  if (TARGET_H8300)
-	    fprintf (file, "%s", names_big[REGNO (x)]);
-	  else
-	    fprintf (file, "%s", names_upper_extended[REGNO (x)]);
+	  fprintf (file, "%s", names_upper_extended[REGNO (x)]);
 	  break;
 	case MEM:
 	  h8300_print_operand (file, x, 0);
@@ -1581,10 +1487,7 @@ h8300_print_operand (FILE *file, rtx x, int code)
       switch (GET_CODE (x))
 	{
 	case REG:
-	  if (TARGET_H8300)
-	    fprintf (file, "%s", names_big[REGNO (x) + 1]);
-	  else
-	    fprintf (file, "%s", names_big[REGNO (x)]);
+	  fprintf (file, "%s", names_big[REGNO (x)]);
 	  break;
 	case MEM:
 	  x = adjust_address (x, HImode, 2);
@@ -1653,8 +1556,7 @@ h8300_print_operand (FILE *file, rtx x, int code)
       if (GET_CODE (x) == CONST_INT)
 	fprintf (file, "#%ld", INTVAL (x) & 0xff);
       else if (GET_CODE (x) == REG)
-	fprintf (file, "%s",
-		 byte_reg (x, TARGET_H8300 ? 2 : 0));
+	fprintf (file, "%s", byte_reg (x, 0));
       else
 	output_operand_lossage ("Expected register or constant integer.");
       break;
@@ -1662,8 +1564,7 @@ h8300_print_operand (FILE *file, rtx x, int code)
       if (GET_CODE (x) == CONST_INT)
 	fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
       else if (GET_CODE (x) == REG)
-	fprintf (file, "%s",
-		 byte_reg (x, TARGET_H8300 ? 3 : 1));
+	fprintf (file, "%s", byte_reg (x, 1));
       else
 	output_operand_lossage ("Expected register or constant integer.");
       break;
@@ -1859,14 +1760,7 @@ h8300_print_operand_address (FILE *file, machine_mode mode, rtx addr)
 
     case CONST_INT:
       {
-	/* Since the H8/300 only has 16-bit pointers, negative values are also
-	   those >= 32768.  This happens for example with pointer minus a
-	   constant.  We don't want to turn (char *p - 2) into
-	   (char *p + 65534) because loop unrolling can build upon this
-	   (IE: char *p + 131068).  */
 	int n = INTVAL (addr);
-	if (TARGET_H8300)
-	  n = (int) (short) n;
 	fprintf (file, "%d", n);
 	break;
       }
@@ -2657,237 +2551,128 @@ compute_mov_length (rtx *operands)
   else
     addr = NULL_RTX;
 
-  if (TARGET_H8300)
-    {
-      unsigned int base_length;
+  unsigned int base_length;
 
-      switch (mode)
-	{
-	case E_QImode:
-	  if (addr == NULL_RTX)
-	    return 2;
+  switch (mode)
+    {
+    case E_QImode:
+      if (addr == NULL_RTX)
+	return 2;
 
-	  /* The eightbit addressing is available only in QImode, so
-	     go ahead and take care of it.  */
-	  if (h8300_eightbit_constant_address_p (addr))
-	    return 2;
+      /* The eightbit addressing is available only in QImode, so
+	 go ahead and take care of it.  */
+      if (h8300_eightbit_constant_address_p (addr))
+	return 2;
 
-	  base_length = 4;
+	  base_length = 8;
 	  break;
 
-	case E_HImode:
-	  if (addr == NULL_RTX)
-	    {
-	      if (REG_P (src))
-		return 2;
+    case E_HImode:
+      if (addr == NULL_RTX)
+	{
+	  if (REG_P (src))
+	    return 2;
 
-	      if (src == const0_rtx)
-		return 2;
+	  if (src == const0_rtx)
+	    return 2;
 
-	      return 4;
-	    }
+	  return 4;
+	}
 
-	  base_length = 4;
-	  break;
+      base_length = 8;
+	break;
 
-	case E_SImode:
-	  if (addr == NULL_RTX)
+    case E_SImode:
+      if (addr == NULL_RTX)
+	{
+	  if (REG_P (src))
 	    {
-	      if (REG_P (src))
+	      if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
 		return 4;
-
-	      if (GET_CODE (src) == CONST_INT)
-		{
-		  if (src == const0_rtx)
-		    return 4;
-
-		  if ((INTVAL (src) & 0xffff) == 0)
-		    return 6;
-
-		  if ((INTVAL (src) & 0xffff) == 0)
-		    return 6;
-
-		  if ((INTVAL (src) & 0xffff)
-		      == ((INTVAL (src) >> 16) & 0xffff))
-		    return 6;
-		}
-	      return 8;
+	      else
+		return 2;
 	    }
 
-	  base_length = 8;
-	  break;
-
-	case E_SFmode:
-	  if (addr == NULL_RTX)
+	  if (GET_CODE (src) == CONST_INT)
 	    {
-	      if (REG_P (src))
-		return 4;
+	      int val = INTVAL (src);
+
+	      if (val == 0)
+		return 2;
 
-	      if (satisfies_constraint_G (src))
+	      if (val == (val & 0x00ff) || val == (val & 0xff00))
 		return 4;
 
-	      return 8;
+	      switch (val & 0xffffffff)
+		{
+		case 0xffffffff:
+		case 0xfffffffe:
+		case 0xfffffffc:
+		case 0x0000ffff:
+		case 0x0000fffe:
+		case 0xffff0000:
+		case 0xfffe0000:
+		case 0x00010000:
+		case 0x00020000:
+		  return 4;
+		}
 	    }
-
-	  base_length = 8;
-	  break;
-
-	default:
-	  gcc_unreachable ();
-	}
-
-      /* Adjust the length based on the addressing mode used.
-	 Specifically, we subtract the difference between the actual
-	 length and the longest one, which is @(d:16,Rs).  For SImode
-	 and SFmode, we double the adjustment because two mov.w are
-	 used to do the job.  */
-
-      /* @Rs+ and @-Rd are 2 bytes shorter than the longest.  */
-      if (GET_CODE (addr) == PRE_DEC
-	  || GET_CODE (addr) == POST_INC)
-	{
-	  if (mode == QImode || mode == HImode)
-	    return base_length - 2;
-	  else
-	    /* In SImode and SFmode, we use two mov.w instructions, so
-	       double the adjustment.  */
-	    return base_length - 4;
+	  return 6;
 	}
 
-      /* @Rs and @Rd are 2 bytes shorter than the longest.  Note that
-	 in SImode and SFmode, the second mov.w involves an address
-	 with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
-	 only 2 bytes.  */
-      if (GET_CODE (addr) == REG)
-	return base_length - 2;
-
-      return base_length;
-    }
-  else
-    {
-      unsigned int base_length;
+      base_length = 10;
+      break;
 
-      switch (mode)
+    case E_SFmode:
+      if (addr == NULL_RTX)
 	{
-	case E_QImode:
-	  if (addr == NULL_RTX)
-	    return 2;
+	  if (REG_P (src))
+   	    return 2;
 
-	  /* The eightbit addressing is available only in QImode, so
-	     go ahead and take care of it.  */
-	  if (h8300_eightbit_constant_address_p (addr))
+	  if (satisfies_constraint_G (src))
 	    return 2;
 
-	  base_length = 8;
-	  break;
-
-	case E_HImode:
-	  if (addr == NULL_RTX)
-	    {
-	      if (REG_P (src))
-		return 2;
-
-	      if (src == const0_rtx)
-		return 2;
-
-	      return 4;
-	    }
-
-	  base_length = 8;
-	  break;
-
-	case E_SImode:
-	  if (addr == NULL_RTX)
-	    {
-	      if (REG_P (src))
-		{
-		  if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG)
-		    return 4;
-		  else
-		    return 2;
-		}
-
-	      if (GET_CODE (src) == CONST_INT)
-		{
-		  int val = INTVAL (src);
-
-		  if (val == 0)
-		    return 2;
+	  return 6;
+	}
 
-		  if (val == (val & 0x00ff) || val == (val & 0xff00))
-		    return 4;
+      base_length = 10;
+	break;
 
-		  switch (val & 0xffffffff)
-		    {
-		    case 0xffffffff:
-		    case 0xfffffffe:
-		    case 0xfffffffc:
-		    case 0x0000ffff:
-		    case 0x0000fffe:
-		    case 0xffff0000:
-		    case 0xfffe0000:
-		    case 0x00010000:
-		    case 0x00020000:
-		      return 4;
-		    }
-		}
-	      return 6;
-	    }
+    default:
+      gcc_unreachable ();
+    }
 
-	  base_length = 10;
-	  break;
+  /* Adjust the length based on the addressing mode used.
+     Specifically, we subtract the difference between the actual
+     length and the longest one, which is @(d:24,ERs).  */
 
-	case E_SFmode:
-	  if (addr == NULL_RTX)
-	    {
-	      if (REG_P (src))
-		return 2;
+  /* @ERs+ and @-ERd are 6 bytes shorter than the longest.  */
+  if (GET_CODE (addr) == PRE_DEC
+      || GET_CODE (addr) == POST_INC)
+    return base_length - 6;
 
-	      if (satisfies_constraint_G (src))
-		return 2;
+  /* @ERs and @ERd are 6 bytes shorter than the longest.  */
+  if (GET_CODE (addr) == REG)
+    return base_length - 6;
 
-	      return 6;
-	    }
+  /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
+     longest.  */
+  if (GET_CODE (addr) == PLUS
+      && GET_CODE (XEXP (addr, 0)) == REG
+      && GET_CODE (XEXP (addr, 1)) == CONST_INT
+      && INTVAL (XEXP (addr, 1)) > -32768
+      && INTVAL (XEXP (addr, 1)) < 32767)
+    return base_length - 4;
 
-	  base_length = 10;
-	  break;
+  /* @aa:16 is 4 bytes shorter than the longest.  */
+  if (h8300_tiny_constant_address_p (addr))
+    return base_length - 4;
 
-	default:
-	  gcc_unreachable ();
-	}
+  /* @aa:24 is 2 bytes shorter than the longest.  */
+  if (CONSTANT_P (addr))
+    return base_length - 2;
 
-      /* Adjust the length based on the addressing mode used.
-	 Specifically, we subtract the difference between the actual
-	 length and the longest one, which is @(d:24,ERs).  */
-
-      /* @ERs+ and @-ERd are 6 bytes shorter than the longest.  */
-      if (GET_CODE (addr) == PRE_DEC
-	  || GET_CODE (addr) == POST_INC)
-	return base_length - 6;
-
-      /* @ERs and @ERd are 6 bytes shorter than the longest.  */
-      if (GET_CODE (addr) == REG)
-	return base_length - 6;
-
-      /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
-	 longest.  */
-      if (GET_CODE (addr) == PLUS
-	  && GET_CODE (XEXP (addr, 0)) == REG
-	  && GET_CODE (XEXP (addr, 1)) == CONST_INT
-	  && INTVAL (XEXP (addr, 1)) > -32768
-	  && INTVAL (XEXP (addr, 1)) < 32767)
-	return base_length - 4;
-
-      /* @aa:16 is 4 bytes shorter than the longest.  */
-      if (h8300_tiny_constant_address_p (addr))
-	return base_length - 4;
-
-      /* @aa:24 is 2 bytes shorter than the longest.  */
-      if (CONSTANT_P (addr))
-	return base_length - 2;
-
-      return base_length;
-    }
+  return base_length;
 }
 
 /* Output an addition insn.  */
@@ -2899,77 +2684,55 @@ output_plussi (rtx *operands)
 
   gcc_assert (mode == SImode);
 
-  if (TARGET_H8300)
-    {
-      if (GET_CODE (operands[2]) == REG)
-	return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
-
-      if (GET_CODE (operands[2]) == CONST_INT)
-	{
-	  HOST_WIDE_INT n = INTVAL (operands[2]);
-
-	  if ((n & 0xffffff) == 0)
-	    return "add\t%z2,%z0";
-	  if ((n & 0xffff) == 0)
-	    return "add\t%y2,%y0\n\taddx\t%z2,%z0";
-	  if ((n & 0xff) == 0)
-	    return "add\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
-	}
-
-      return "add\t%w2,%w0\n\taddx\t%x2,%x0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
-    }
-  else
+  if (GET_CODE (operands[2]) == CONST_INT
+      && register_operand (operands[1], VOIDmode))
     {
-      if (GET_CODE (operands[2]) == CONST_INT
-	  && register_operand (operands[1], VOIDmode))
-	{
-	  HOST_WIDE_INT intval = INTVAL (operands[2]);
+      HOST_WIDE_INT intval = INTVAL (operands[2]);
 
-	  if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
-	    return "add.l\t%S2,%S0";
-	  if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
-	    return "sub.l\t%G2,%S0";
+      if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
+	return "add.l\t%S2,%S0";
+      if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
+	return "sub.l\t%G2,%S0";
 
-	  /* See if we can finish with 2 bytes.  */
+      /* See if we can finish with 2 bytes.  */
 
-	  switch ((unsigned int) intval & 0xffffffff)
-	    {
-	    case 0x00000001:
-	    case 0x00000002:
-	    case 0x00000004:
-	      return "adds\t%2,%S0";
-
-	    case 0xffffffff:
-	    case 0xfffffffe:
-	    case 0xfffffffc:
-	      return "subs\t%G2,%S0";
-
-	    case 0x00010000:
-	    case 0x00020000:
-	      operands[2] = GEN_INT (intval >> 16);
-	      return "inc.w\t%2,%e0";
-
-	    case 0xffff0000:
-	    case 0xfffe0000:
-	      operands[2] = GEN_INT (intval >> 16);
-	      return "dec.w\t%G2,%e0";
-	    }
-
-	  /* See if we can finish with 4 bytes.  */
-	  if ((intval & 0xffff) == 0)
-	    {
-	      operands[2] = GEN_INT (intval >> 16);
-	      return "add.w\t%2,%e0";
-	    }
+      switch ((unsigned int) intval & 0xffffffff)
+	{
+	case 0x00000001:
+	case 0x00000002:
+	case 0x00000004:
+	  return "adds\t%2,%S0";
+
+	case 0xffffffff:
+	case 0xfffffffe:
+	case 0xfffffffc:
+	  return "subs\t%G2,%S0";
+
+	case 0x00010000:
+	case 0x00020000:
+	  operands[2] = GEN_INT (intval >> 16);
+	  return "inc.w\t%2,%e0";
+
+	case 0xffff0000:
+	case 0xfffe0000:
+	  operands[2] = GEN_INT (intval >> 16);
+	  return "dec.w\t%G2,%e0";
 	}
 
-      if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
+      /* See if we can finish with 4 bytes.  */
+      if ((intval & 0xffff) == 0)
 	{
-	  operands[2] = GEN_INT (-INTVAL (operands[2]));
-	  return "sub.l\t%S2,%S0";
+	  operands[2] = GEN_INT (intval >> 16);
+	  return "add.w\t%2,%e0";
 	}
-      return "add.l\t%S2,%S0";
     }
+
+  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
+    {
+      operands[2] = GEN_INT (-INTVAL (operands[2]));
+      return "sub.l\t%S2,%S0";
+    }
+  return "add.l\t%S2,%S0";
 }
 
 /* ??? It would be much easier to add the h8sx stuff if a single function
@@ -2983,74 +2746,51 @@ compute_plussi_length (rtx *operands)
 
   gcc_assert (mode == SImode);
 
-  if (TARGET_H8300)
+  if (GET_CODE (operands[2]) == CONST_INT
+      && register_operand (operands[1], VOIDmode))
     {
-      if (GET_CODE (operands[2]) == REG)
-	return 6;
+      HOST_WIDE_INT intval = INTVAL (operands[2]);
 
-      if (GET_CODE (operands[2]) == CONST_INT)
-	{
-	  HOST_WIDE_INT n = INTVAL (operands[2]);
+      if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
+	return 2;
+      if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
+	return 2;
 
-	  if ((n & 0xffffff) == 0)
-	    return 2;
-	  if ((n & 0xffff) == 0)
-	    return 4;
-	  if ((n & 0xff) == 0)
-	    return 6;
-	}
+      /* See if we can finish with 2 bytes.  */
 
-      return 8;
-    }
-  else
-    {
-      if (GET_CODE (operands[2]) == CONST_INT
-	  && register_operand (operands[1], VOIDmode))
+      switch ((unsigned int) intval & 0xffffffff)
 	{
-	  HOST_WIDE_INT intval = INTVAL (operands[2]);
-
-	  if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
-	    return 2;
-	  if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
-	    return 2;
-
-	  /* See if we can finish with 2 bytes.  */
-
-	  switch ((unsigned int) intval & 0xffffffff)
-	    {
-	    case 0x00000001:
-	    case 0x00000002:
-	    case 0x00000004:
-	      return 2;
-
-	    case 0xffffffff:
-	    case 0xfffffffe:
-	    case 0xfffffffc:
-	      return 2;
-
-	    case 0x00010000:
-	    case 0x00020000:
-	      return 2;
-
-	    case 0xffff0000:
-	    case 0xfffe0000:
-	      return 2;
-	    }
-
-	  /* See if we can finish with 4 bytes.  */
-	  if ((intval & 0xffff) == 0)
-	    return 4;
+	case 0x00000001:
+	case 0x00000002:
+	case 0x00000004:
+	  return 2;
+
+	case 0xffffffff:
+	case 0xfffffffe:
+	case 0xfffffffc:
+	  return 2;
+
+	case 0x00010000:
+	case 0x00020000:
+	  return 2;
+
+	case 0xffff0000:
+	case 0xfffe0000:
+	  return 2;
 	}
 
-      if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
-	return h8300_length_from_table (operands[0],
-					GEN_INT (-INTVAL (operands[2])),
-					&addl_length_table);
-      else
-	return h8300_length_from_table (operands[0], operands[2],
-					&addl_length_table);
-      return 6;
+      /* See if we can finish with 4 bytes.  */
+      if ((intval & 0xffff) == 0)
+	return 4;
     }
+
+  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
+    return h8300_length_from_table (operands[0],
+				    GEN_INT (-INTVAL (operands[2])),
+				    &addl_length_table);
+  else
+    return h8300_length_from_table (operands[0], operands[2],
+				    &addl_length_table);
 }
 
 /* Compute which flag bits are valid after an addition insn.  */
@@ -3062,52 +2802,45 @@ compute_plussi_cc (rtx *operands)
 
   gcc_assert (mode == SImode);
 
-  if (TARGET_H8300)
-    {
-      return CC_CLOBBER;
-    }
-  else
+  if (GET_CODE (operands[2]) == CONST_INT
+      && register_operand (operands[1], VOIDmode))
     {
-      if (GET_CODE (operands[2]) == CONST_INT
-	  && register_operand (operands[1], VOIDmode))
-	{
-	  HOST_WIDE_INT intval = INTVAL (operands[2]);
+      HOST_WIDE_INT intval = INTVAL (operands[2]);
 
-	  if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
-	    return CC_SET_ZN;
-	  if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
-	    return CC_SET_ZN;
+      if (TARGET_H8300SX && (intval >= 1 && intval <= 7))
+	return CC_SET_ZN;
+      if (TARGET_H8300SX && (intval >= -7 && intval <= -1))
+	return CC_SET_ZN;
 
-	  /* See if we can finish with 2 bytes.  */
+      /* See if we can finish with 2 bytes.  */
 
-	  switch ((unsigned int) intval & 0xffffffff)
-	    {
-	    case 0x00000001:
-	    case 0x00000002:
-	    case 0x00000004:
-	      return CC_NONE_0HIT;
-
-	    case 0xffffffff:
-	    case 0xfffffffe:
-	    case 0xfffffffc:
-	      return CC_NONE_0HIT;
-
-	    case 0x00010000:
-	    case 0x00020000:
-	      return CC_CLOBBER;
-
-	    case 0xffff0000:
-	    case 0xfffe0000:
-	      return CC_CLOBBER;
-	    }
-
-	  /* See if we can finish with 4 bytes.  */
-	  if ((intval & 0xffff) == 0)
-	    return CC_CLOBBER;
+      switch ((unsigned int) intval & 0xffffffff)
+	{
+	case 0x00000001:
+	case 0x00000002:
+	case 0x00000004:
+	  return CC_NONE_0HIT;
+
+	case 0xffffffff:
+	case 0xfffffffe:
+	case 0xfffffffc:
+	  return CC_NONE_0HIT;
+
+	case 0x00010000:
+	case 0x00020000:
+	  return CC_CLOBBER;
+
+	case 0xffff0000:
+	case 0xfffe0000:
+	  return CC_CLOBBER;
 	}
 
-      return CC_SET_ZN;
+      /* See if we can finish with 4 bytes.  */
+      if ((intval & 0xffff) == 0)
+	return CC_CLOBBER;
     }
+
+  return CC_SET_ZN;
 }
 
 /* Output a logical insn.  */
@@ -3132,8 +2865,6 @@ output_logical_op (machine_mode mode, rtx *operands)
   /* Break up DET into pieces.  */
   const unsigned HOST_WIDE_INT b0 = (det >>  0) & 0xff;
   const unsigned HOST_WIDE_INT b1 = (det >>  8) & 0xff;
-  const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
-  const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
   const unsigned HOST_WIDE_INT w0 = (det >>  0) & 0xffff;
   const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
   int lower_half_easy_p = 0;
@@ -3161,9 +2892,7 @@ output_logical_op (machine_mode mode, rtx *operands)
     {
     case E_HImode:
       /* First, see if we can finish with one insn.  */
-      if ((TARGET_H8300H || TARGET_H8300S)
-	  && b0 != 0
-	  && b1 != 0)
+      if (b0 != 0 && b1 != 0)
 	{
 	  sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname);
 	  output_asm_insn (insn_buf, operands);
@@ -3185,24 +2914,20 @@ output_logical_op (machine_mode mode, rtx *operands)
 	}
       break;
     case E_SImode:
-      if (TARGET_H8300H || TARGET_H8300S)
-	{
-	  /* Determine if the lower half can be taken care of in no more
-	     than two bytes.  */
-	  lower_half_easy_p = (b0 == 0
-			       || b1 == 0
-			       || (code != IOR && w0 == 0xffff));
-
-	  /* Determine if the upper half can be taken care of in no more
-	     than two bytes.  */
-	  upper_half_easy_p = ((code != IOR && w1 == 0xffff)
-			       || (code == AND && w1 == 0xff00));
-	}
+      /* Determine if the lower half can be taken care of in no more
+	 than two bytes.  */
+      lower_half_easy_p = (b0 == 0
+			   || b1 == 0
+			   || (code != IOR && w0 == 0xffff));
+
+       /* Determine if the upper half can be taken care of in no more
+	  than two bytes.  */
+      upper_half_easy_p = ((code != IOR && w1 == 0xffff)
+			   || (code == AND && w1 == 0xff00));
 
       /* Check if doing everything with one insn is no worse than
 	 using multiple insns.  */
-      if ((TARGET_H8300H || TARGET_H8300S)
-	  && w0 != 0 && w1 != 0
+      if (w0 != 0 && w1 != 0
 	  && !(lower_half_easy_p && upper_half_easy_p)
 	  && !(code == IOR && w1 == 0xffff
 	       && (w0 & 0x8000) != 0 && lower_half_easy_p))
@@ -3218,14 +2943,11 @@ output_logical_op (machine_mode mode, rtx *operands)
 	     1) the special insn (in case of AND or XOR),
 	     2) the word-wise insn, and
 	     3) The byte-wise insn.  */
-	  if (w0 == 0xffff
-	      && (TARGET_H8300 ? (code == AND) : (code != IOR)))
+	  if (w0 == 0xffff && (code != IOR))
 	    output_asm_insn ((code == AND)
 			     ? "sub.w\t%f0,%f0" : "not.w\t%f0",
 			     operands);
-	  else if ((TARGET_H8300H || TARGET_H8300S)
-		   && (b0 != 0)
-		   && (b1 != 0))
+	  else if ((b0 != 0) && (b1 != 0))
 	    {
 	      sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname);
 	      output_asm_insn (insn_buf, operands);
@@ -3244,25 +2966,22 @@ output_logical_op (machine_mode mode, rtx *operands)
 		}
 	    }
 
-	  if ((w1 == 0xffff)
-	      && (TARGET_H8300 ? (code == AND) : (code != IOR)))
+	  if ((w1 == 0xffff) && (code != IOR))
 	    output_asm_insn ((code == AND)
 			     ? "sub.w\t%e0,%e0" : "not.w\t%e0",
 			     operands);
-	  else if ((TARGET_H8300H || TARGET_H8300S)
-		   && code == IOR
+	  else if (code == IOR
 		   && w1 == 0xffff
 		   && (w0 & 0x8000) != 0)
 	    {
 	      output_asm_insn ("exts.l\t%S0", operands);
 	    }
-	  else if ((TARGET_H8300H || TARGET_H8300S)
-		   && code == AND
+	  else if (code == AND
 		   && w1 == 0xff00)
 	    {
 	      output_asm_insn ("extu.w\t%e0", operands);
 	    }
-	  else if (TARGET_H8300H || TARGET_H8300S)
+	  else
 	    {
 	      if (w1 != 0)
 		{
@@ -3270,19 +2989,6 @@ output_logical_op (machine_mode mode, rtx *operands)
 		  output_asm_insn (insn_buf, operands);
 		}
 	    }
-	  else
-	    {
-	      if (b2 != 0)
-		{
-		  sprintf (insn_buf, "%s\t%%y2,%%y0", opname);
-		  output_asm_insn (insn_buf, operands);
-		}
-	      if (b3 != 0)
-		{
-		  sprintf (insn_buf, "%s\t%%z2,%%z0", opname);
-		  output_asm_insn (insn_buf, operands);
-		}
-	    }
 	}
       break;
     default:
@@ -3313,8 +3019,6 @@ compute_logical_op_length (machine_mode mode, rtx *operands)
   /* Break up DET into pieces.  */
   const unsigned HOST_WIDE_INT b0 = (det >>  0) & 0xff;
   const unsigned HOST_WIDE_INT b1 = (det >>  8) & 0xff;
-  const unsigned HOST_WIDE_INT b2 = (det >> 16) & 0xff;
-  const unsigned HOST_WIDE_INT b3 = (det >> 24) & 0xff;
   const unsigned HOST_WIDE_INT w0 = (det >>  0) & 0xffff;
   const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff;
   int lower_half_easy_p = 0;
@@ -3326,9 +3030,7 @@ compute_logical_op_length (machine_mode mode, rtx *operands)
     {
     case E_HImode:
       /* First, see if we can finish with one insn.  */
-      if ((TARGET_H8300H || TARGET_H8300S)
-	  && b0 != 0
-	  && b1 != 0)
+      if (b0 != 0 && b1 != 0)
 	{
 	  length = h8300_length_from_table (operands[1], operands[2],
 					    &logicw_length_table);
@@ -3345,24 +3047,20 @@ compute_logical_op_length (machine_mode mode, rtx *operands)
 	}
       break;
     case E_SImode:
-      if (TARGET_H8300H || TARGET_H8300S)
-	{
-	  /* Determine if the lower half can be taken care of in no more
-	     than two bytes.  */
-	  lower_half_easy_p = (b0 == 0
-			       || b1 == 0
-			       || (code != IOR && w0 == 0xffff));
-
-	  /* Determine if the upper half can be taken care of in no more
-	     than two bytes.  */
-	  upper_half_easy_p = ((code != IOR && w1 == 0xffff)
-			       || (code == AND && w1 == 0xff00));
-	}
+      /* Determine if the lower half can be taken care of in no more
+	 than two bytes.  */
+      lower_half_easy_p = (b0 == 0
+			   || b1 == 0
+			   || (code != IOR && w0 == 0xffff));
+
+      /* Determine if the upper half can be taken care of in no more
+	 than two bytes.  */
+      upper_half_easy_p = ((code != IOR && w1 == 0xffff)
+			   || (code == AND && w1 == 0xff00));
 
       /* Check if doing everything with one insn is no worse than
 	 using multiple insns.  */
-      if ((TARGET_H8300H || TARGET_H8300S)
-	  && w0 != 0 && w1 != 0
+      if (w0 != 0 && w1 != 0
 	  && !(lower_half_easy_p && upper_half_easy_p)
 	  && !(code == IOR && w1 == 0xffff
 	       && (w0 & 0x8000) != 0 && lower_half_easy_p))
@@ -3378,14 +3076,11 @@ compute_logical_op_length (machine_mode mode, rtx *operands)
 	     1) the special insn (in case of AND or XOR),
 	     2) the word-wise insn, and
 	     3) The byte-wise insn.  */
-	  if (w0 == 0xffff
-	      && (TARGET_H8300 ? (code == AND) : (code != IOR)))
+	  if (w0 == 0xffff && (code != IOR))
 	    {
 	      length += 2;
 	    }
-	  else if ((TARGET_H8300H || TARGET_H8300S)
-		   && (b0 != 0)
-		   && (b1 != 0))
+	  else if ((b0 != 0) && (b1 != 0))
 	    {
 	      length += 4;
 	    }
@@ -3398,37 +3093,25 @@ compute_logical_op_length (machine_mode mode, rtx *operands)
 		length += 2;
 	    }
 
-	  if (w1 == 0xffff
-	      && (TARGET_H8300 ? (code == AND) : (code != IOR)))
+	  if (w1 == 0xffff && (code != IOR))
 	    {
 	      length += 2;
 	    }
-	  else if ((TARGET_H8300H || TARGET_H8300S)
-		   && code == IOR
+	  else if (code == IOR
 		   && w1 == 0xffff
 		   && (w0 & 0x8000) != 0)
 	    {
 	      length += 2;
 	    }
-	  else if ((TARGET_H8300H || TARGET_H8300S)
-		   && code == AND
-		   && w1 == 0xff00)
+	  else if (code == AND && w1 == 0xff00)
 	    {
 	      length += 2;
 	    }
-	  else if (TARGET_H8300H || TARGET_H8300S)
+	  else
 	    {
 	      if (w1 != 0)
 		length += 4;
 	    }
-	  else
-	    {
-	      if (b2 != 0)
-		length += 2;
-
-	      if (b3 != 0)
-		length += 2;
-	    }
 	}
       break;
     default:
@@ -3470,32 +3153,26 @@ compute_logical_op_cc (machine_mode mode, rtx *operands)
     {
     case E_HImode:
       /* First, see if we can finish with one insn.  */
-      if ((TARGET_H8300H || TARGET_H8300S)
-	  && b0 != 0
-	  && b1 != 0)
+      if (b0 != 0 && b1 != 0)
 	{
 	  cc = CC_SET_ZNV;
 	}
       break;
     case E_SImode:
-      if (TARGET_H8300H || TARGET_H8300S)
-	{
-	  /* Determine if the lower half can be taken care of in no more
-	     than two bytes.  */
-	  lower_half_easy_p = (b0 == 0
-			       || b1 == 0
-			       || (code != IOR && w0 == 0xffff));
-
-	  /* Determine if the upper half can be taken care of in no more
-	     than two bytes.  */
-	  upper_half_easy_p = ((code != IOR && w1 == 0xffff)
-			       || (code == AND && w1 == 0xff00));
-	}
+      /* Determine if the lower half can be taken care of in no more
+	 than two bytes.  */
+      lower_half_easy_p = (b0 == 0
+			   || b1 == 0
+			   || (code != IOR && w0 == 0xffff));
+
+      /* Determine if the upper half can be taken care of in no more
+         than two bytes.  */
+      upper_half_easy_p = ((code != IOR && w1 == 0xffff)
+			   || (code == AND && w1 == 0xff00));
 
       /* Check if doing everything with one insn is no worse than
 	 using multiple insns.  */
-      if ((TARGET_H8300H || TARGET_H8300S)
-	  && w0 != 0 && w1 != 0
+      if (w0 != 0 && w1 != 0
 	  && !(lower_half_easy_p && upper_half_easy_p)
 	  && !(code == IOR && w1 == 0xffff
 	       && (w0 & 0x8000) != 0 && lower_half_easy_p))
@@ -3504,8 +3181,7 @@ compute_logical_op_cc (machine_mode mode, rtx *operands)
 	}
       else
 	{
-	  if ((TARGET_H8300H || TARGET_H8300S)
-	      && code == IOR
+	  if (code == IOR
 	      && w1 == 0xffff
 	      && (w0 & 0x8000) != 0)
 	    {
@@ -3916,8 +3592,7 @@ static void get_shift_alg (enum shift_type,
 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the
    best algorithm for doing the shift.  The assembler code is stored
    in the pointers in INFO.  We achieve the maximum efficiency in most
-   cases when !TARGET_H8300.  In case of TARGET_H8300, shifts in
-   SImode in particular have a lot of room to optimize.
+   cases.
 
    We first determine the strategy of the shift algorithm by a table
    lookup.  If that tells us to use a hand crafted assembly code, we
@@ -3931,10 +3606,7 @@ get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
 {
   enum h8_cpu cpu;
 
-  /* Find the target CPU.  */
-  if (TARGET_H8300)
-    cpu = H8_300;
-  else if (TARGET_H8300S)
+  if (TARGET_H8300S)
     cpu = H8_S;
   else
     cpu = H8_300H;
@@ -4008,16 +3680,10 @@ get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
 	  switch (shift_type)
 	    {
 	    case SHIFT_ASHIFT:
-	      if (TARGET_H8300)
-		info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.b\t%t0\n\trotr.b\t%s0\n\tand.b\t#0x80,%s0";
-	      else
-		info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
+	      info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0";
 	      goto end;
 	    case SHIFT_LSHIFTRT:
-	      if (TARGET_H8300)
-		info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\trotl.b\t%t0\n\tand.b\t#0x01,%t0";
-	      else
-		info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
+	      info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0";
 	      goto end;
 	    case SHIFT_ASHIFTRT:
 	      info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0";
@@ -4035,29 +3701,12 @@ get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
 	      info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0";
 	      goto end;
 	    case SHIFT_LSHIFTRT:
-	      if (TARGET_H8300)
-		{
-		  info->special = "mov.b\t%t0,%s0\n\tsub.b\t%t0,%t0";
-		  info->shift1  = "shlr.b\t%s0";
-		  info->cc_inline = CC_SET_ZNV;
-		}
-	      else
-		{
-		  info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
-		  info->cc_special = CC_SET_ZNV;
-		}
+	      info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0";
+	      info->cc_special = CC_SET_ZNV;
 	      goto end;
 	    case SHIFT_ASHIFTRT:
-	      if (TARGET_H8300)
-		{
-		  info->special = "mov.b\t%t0,%s0\n\tbld\t#7,%s0\n\tsubx\t%t0,%t0";
-		  info->shift1  = "shar.b\t%s0";
-		}
-	      else
-		{
-		  info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
-		  info->cc_special = CC_SET_ZNV;
-		}
+	      info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0";
+	      info->cc_special = CC_SET_ZNV;
 	      goto end;
 	    }
 	}
@@ -4066,17 +3715,11 @@ get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
 	  switch (shift_type)
 	    {
 	    case SHIFT_ASHIFT:
-	      if (TARGET_H8300)
-		info->special = "mov.b\t%s0,%t0\n\trotr.b\t%t0\n\trotr.b\t%t0\n\tand.b\t#0xC0,%t0\n\tsub.b\t%s0,%s0";
-	      goto end;
 	    case SHIFT_LSHIFTRT:
-	      if (TARGET_H8300)
-		info->special = "mov.b\t%t0,%s0\n\trotl.b\t%s0\n\trotl.b\t%s0\n\tand.b\t#3,%s0\n\tsub.b\t%t0,%t0";
+	      goto end;
 	      goto end;
 	    case SHIFT_ASHIFTRT:
-	      if (TARGET_H8300)
-		info->special = "mov.b\t%t0,%s0\n\tshll.b\t%s0\n\tsubx.b\t%t0,%t0\n\tshll.b\t%s0\n\tmov.b\t%t0,%s0\n\tbst.b\t#0,%s0";
-	      else if (TARGET_H8300H)
+	      if (TARGET_H8300H)
 		{
 		  info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0";
 		  info->cc_special = CC_SET_ZNV;
@@ -4104,25 +3747,7 @@ get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
       gcc_unreachable ();
 
     case SIshift:
-      if (TARGET_H8300 && count >= 8 && count <= 9)
-	{
-	  info->remainder = count - 8;
-
-	  switch (shift_type)
-	    {
-	    case SHIFT_ASHIFT:
-	      info->special = "mov.b\t%y0,%z0\n\tmov.b\t%x0,%y0\n\tmov.b\t%w0,%x0\n\tsub.b\t%w0,%w0";
-	      goto end;
-	    case SHIFT_LSHIFTRT:
-	      info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tsub.b\t%z0,%z0";
-	      info->shift1  = "shlr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0";
-	      goto end;
-	    case SHIFT_ASHIFTRT:
-	      info->special = "mov.b\t%x0,%w0\n\tmov.b\t%y0,%x0\n\tmov.b\t%z0,%y0\n\tshll\t%z0\n\tsubx\t%z0,%z0";
-	      goto end;
-	    }
-	}
-      else if (count == 8 && !TARGET_H8300)
+      if (count == 8)
 	{
 	  switch (shift_type)
 	    {
@@ -4137,21 +3762,7 @@ get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
 	      goto end;
 	    }
 	}
-      else if (count == 15 && TARGET_H8300)
-	{
-	  switch (shift_type)
-	    {
-	    case SHIFT_ASHIFT:
-	      gcc_unreachable ();
-	    case SHIFT_LSHIFTRT:
-	      info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\txor\t%y0,%y0\n\txor\t%z0,%z0\n\trotxl\t%w0\n\trotxl\t%x0\n\trotxl\t%y0";
-	      goto end;
-	    case SHIFT_ASHIFTRT:
-	      info->special = "bld\t#7,%z0\n\tmov.w\t%e0,%f0\n\trotxl\t%w0\n\trotxl\t%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
-	      goto end;
-	    }
-	}
-      else if (count == 15 && !TARGET_H8300)
+      else if (count == 15)
 	{
 	  switch (shift_type)
 	    {
@@ -4167,8 +3778,7 @@ get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
 	      gcc_unreachable ();
 	    }
 	}
-      else if ((TARGET_H8300 && count >= 16 && count <= 20)
-	       || (TARGET_H8300H && count >= 16 && count <= 19)
+      else if ((TARGET_H8300H && count >= 16 && count <= 19)
 	       || (TARGET_H8300S && count >= 16 && count <= 21))
 	{
 	  info->remainder = count - 16;
@@ -4177,55 +3787,14 @@ get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
 	    {
 	    case SHIFT_ASHIFT:
 	      info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0";
-	      if (TARGET_H8300)
-		info->shift1 = "add.w\t%e0,%e0";
 	      goto end;
 	    case SHIFT_LSHIFTRT:
-	      if (TARGET_H8300)
-		{
-		  info->special = "mov.w\t%e0,%f0\n\tsub.w\t%e0,%e0";
-		  info->shift1  = "shlr\t%x0\n\trotxr\t%w0";
-		}
-	      else
-		{
-		  info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
-		  info->cc_special = CC_SET_ZNV;
-		}
-	      goto end;
-	    case SHIFT_ASHIFTRT:
-	      if (TARGET_H8300)
-		{
-		  info->special = "mov.w\t%e0,%f0\n\tshll\t%z0\n\tsubx\t%z0,%z0\n\tmov.b\t%z0,%y0";
-		  info->shift1  = "shar\t%x0\n\trotxr\t%w0";
-		}
-	      else
-		{
-		  info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
-		  info->cc_special = CC_SET_ZNV;
-		}
-	      goto end;
-	    }
-	}
-      else if (TARGET_H8300 && count >= 24 && count <= 28)
-	{
-	  info->remainder = count - 24;
-
-	  switch (shift_type)
-	    {
-	    case SHIFT_ASHIFT:
-	      info->special = "mov.b\t%w0,%z0\n\tsub.b\t%y0,%y0\n\tsub.w\t%f0,%f0";
-	      info->shift1  = "shll.b\t%z0";
-	      info->cc_inline = CC_SET_ZNV;
-	      goto end;
-	    case SHIFT_LSHIFTRT:
-	      info->special = "mov.b\t%z0,%w0\n\tsub.b\t%x0,%x0\n\tsub.w\t%e0,%e0";
-	      info->shift1  = "shlr.b\t%w0";
-	      info->cc_inline = CC_SET_ZNV;
+	      info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0";
+	      info->cc_special = CC_SET_ZNV;
 	      goto end;
 	    case SHIFT_ASHIFTRT:
-	      info->special = "mov.b\t%z0,%w0\n\tbld\t#7,%w0\n\tsubx\t%x0,%x0\n\tsubx\t%y0,%y0\n\tsubx\t%z0,%z0";
-	      info->shift1  = "shar.b\t%w0";
-	      info->cc_inline = CC_SET_ZNV;
+	      info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0";
+	      info->cc_special = CC_SET_ZNV;
 	      goto end;
 	    }
 	}
@@ -4249,7 +3818,7 @@ get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
 	      goto end;
 	    }
 	}
-      else if (!TARGET_H8300 && count == 28)
+      else if (count == 28)
 	{
 	  switch (shift_type)
 	    {
@@ -4272,7 +3841,7 @@ get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
 	      gcc_unreachable ();
 	    }
 	}
-      else if (!TARGET_H8300 && count == 29)
+      else if (count == 29)
 	{
 	  switch (shift_type)
 	    {
@@ -4298,7 +3867,7 @@ get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
 	      gcc_unreachable ();
 	    }
 	}
-      else if (!TARGET_H8300 && count == 30)
+      else if (count == 30)
 	{
 	  switch (shift_type)
 	    {
@@ -4320,38 +3889,20 @@ get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode,
 	}
       else if (count == 31)
 	{
-	  if (TARGET_H8300)
-	    {
-	      switch (shift_type)
-		{
-		case SHIFT_ASHIFT:
-		  info->special = "sub.w\t%e0,%e0\n\tshlr\t%w0\n\tmov.w\t%e0,%f0\n\trotxr\t%z0";
-		  goto end;
-		case SHIFT_LSHIFTRT:
-		  info->special = "sub.w\t%f0,%f0\n\tshll\t%z0\n\tmov.w\t%f0,%e0\n\trotxl\t%w0";
-		  goto end;
-		case SHIFT_ASHIFTRT:
-		  info->special = "shll\t%z0\n\tsubx\t%w0,%w0\n\tmov.b\t%w0,%x0\n\tmov.w\t%f0,%e0";
-		  goto end;
-		}
-	    }
-	  else
+	  switch (shift_type)
 	    {
-	      switch (shift_type)
-		{
-		case SHIFT_ASHIFT:
-		  info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
-		  info->cc_special = CC_SET_ZNV;
-		  goto end;
-		case SHIFT_LSHIFTRT:
-		  info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
-		  info->cc_special = CC_SET_ZNV;
-		  goto end;
-		case SHIFT_ASHIFTRT:
-		  info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
-		  info->cc_special = CC_SET_ZNV;
-		  goto end;
-		}
+	    case SHIFT_ASHIFT:
+	      info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0";
+	      info->cc_special = CC_SET_ZNV;
+	      goto end;
+	    case SHIFT_LSHIFTRT:
+	      info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0";
+	      info->cc_special = CC_SET_ZNV;
+	      goto end;
+	    case SHIFT_ASHIFTRT:
+	      info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0";
+	      info->cc_special = CC_SET_ZNV;
+	      goto end;
 	    }
 	}
       gcc_unreachable ();
@@ -4378,9 +3929,7 @@ h8300_shift_needs_scratch_p (int count, machine_mode mode)
     return 1;
 
   /* Find out the target CPU.  */
-  if (TARGET_H8300)
-    cpu = H8_300;
-  else if (TARGET_H8300S)
+  if (TARGET_H8300S)
     cpu = H8_S;
   else
     cpu = H8_300H;
@@ -4530,7 +4079,6 @@ output_a_shift (rtx *operands)
 	    break;
 
 	  case E_HImode:
-	    gcc_assert (TARGET_H8300H || TARGET_H8300S);
 	    sprintf (insn_buf, "and.w\t#%d,%%T0", mask);
 	    break;
 
@@ -4704,7 +4252,6 @@ compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
 		wlength += 2;
 		break;
 	      case E_SImode:
-		gcc_assert (!TARGET_H8300);
 		wlength += 3;
 		break;
 	      default:
@@ -4970,8 +4517,7 @@ output_a_rotate (enum rtx_code code, rtx *operands)
 
   /* See if a byte swap (in HImode) or a word swap (in SImode) can
      boost up the rotation.  */
-  if ((mode == HImode && TARGET_H8300 && amount >= 5)
-      || (mode == HImode && TARGET_H8300H && amount >= 6)
+  if ((mode == HImode && TARGET_H8300H && amount >= 6)
       || (mode == HImode && TARGET_H8300S && amount == 8)
       || (mode == SImode && TARGET_H8300H && amount >= 10)
       || (mode == SImode && TARGET_H8300S && amount >= 13))
@@ -5044,8 +4590,7 @@ compute_a_rotate_length (rtx *operands)
 
   /* See if a byte swap (in HImode) or a word swap (in SImode) can
      boost up the rotation.  */
-  if ((mode == HImode && TARGET_H8300 && amount >= 5)
-      || (mode == HImode && TARGET_H8300H && amount >= 6)
+  if ((mode == HImode && TARGET_H8300H && amount >= 6)
       || (mode == HImode && TARGET_H8300S && amount == 8)
       || (mode == SImode && TARGET_H8300H && amount >= 10)
       || (mode == SImode && TARGET_H8300S && amount >= 13))
@@ -5061,7 +4606,7 @@ compute_a_rotate_length (rtx *operands)
 
   /* The H8/300 uses three insns to rotate one bit, taking 6
      length.  */
-  length += amount * ((TARGET_H8300 && mode == HImode) ? 6 : 2);
+  length += amount * 2;
 
   return length;
 }
@@ -5395,41 +4940,24 @@ h8300_encode_section_info (tree decl, rtx rtl, int first)
 const char *
 output_simode_bld (int bild, rtx operands[])
 {
-  if (TARGET_H8300)
-    {
-      /* Clear the destination register.  */
-      output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
+  /* Determine if we can clear the destination first.  */
+  int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
+		     && REGNO (operands[0]) != REGNO (operands[1]));
 
-      /* Now output the bit load or bit inverse load, and store it in
-	 the destination.  */
-      if (bild)
-	output_asm_insn ("bild\t%Z2,%Y1", operands);
-      else
-	output_asm_insn ("bld\t%Z2,%Y1", operands);
+  if (clear_first)
+    output_asm_insn ("sub.l\t%S0,%S0", operands);
 
-      output_asm_insn ("bst\t#0,%w0", operands);
-    }
+  /* Output the bit load or bit inverse load.  */
+  if (bild)
+    output_asm_insn ("bild\t%Z2,%Y1", operands);
   else
-    {
-      /* Determine if we can clear the destination first.  */
-      int clear_first = (REG_P (operands[0]) && REG_P (operands[1])
-			 && REGNO (operands[0]) != REGNO (operands[1]));
+    output_asm_insn ("bld\t%Z2,%Y1", operands);
 
-      if (clear_first)
-	output_asm_insn ("sub.l\t%S0,%S0", operands);
+  if (!clear_first)
+    output_asm_insn ("xor.l\t%S0,%S0", operands);
 
-      /* Output the bit load or bit inverse load.  */
-      if (bild)
-	output_asm_insn ("bild\t%Z2,%Y1", operands);
-      else
-	output_asm_insn ("bld\t%Z2,%Y1", operands);
-
-      if (!clear_first)
-	output_asm_insn ("xor.l\t%S0,%S0", operands);
-
-      /* Perform the bit store.  */
-      output_asm_insn ("rotxl.l\t%S0", operands);
-    }
+  /* Perform the bit store.  */
+  output_asm_insn ("rotxl.l\t%S0", operands);
 
   /* All done.  */
   return "";
@@ -5478,7 +5006,7 @@ h8300_eightbit_constant_address_p (rtx x)
   addr = INTVAL (x);
 
   return (0
-	  || ((TARGET_H8300 || TARGET_NORMAL_MODE) && IN_RANGE (addr, n1, n2))
+	  || (TARGET_NORMAL_MODE && IN_RANGE (addr, n1, n2))
 	  || (TARGET_H8300H && IN_RANGE (addr, h1, h2))
 	  || (TARGET_H8300S && IN_RANGE (addr, s1, s2)));
 }
@@ -5728,14 +5256,9 @@ h8300_legitimate_address_p (machine_mode mode, rtx x, bool strict)
 static bool
 h8300_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
 {
-  if (TARGET_H8300)
-    /* If an even reg, then anything goes.  Otherwise the mode must be
-       QI or HI.  */
-    return ((regno & 1) == 0) || (mode == HImode) || (mode == QImode);
-  else
-    /* MAC register can only be of SImode.  Otherwise, anything
-       goes.  */
-    return regno == MAC_REG ? mode == SImode : 1;
+  /* MAC register can only be of SImode.  Otherwise, anything
+     goes.  */
+  return regno == MAC_REG ? mode == SImode : 1;
 }
 
 /* Implement TARGET_MODES_TIEABLE_P.  */
@@ -5746,10 +5269,10 @@ h8300_modes_tieable_p (machine_mode mode1, machine_mode mode2)
   return (mode1 == mode2
 	  || ((mode1 == QImode
 	       || mode1 == HImode
-	       || ((TARGET_H8300H || TARGET_H8300S) && mode1 == SImode))
+	       || mode1 == SImode)
 	      && (mode2 == QImode
 		  || mode2 == HImode
-		  || ((TARGET_H8300H || TARGET_H8300S) && mode2 == SImode))));
+		  || mode2 == SImode)));
 }
 
 /* Helper function for the move patterns.  Make sure a move is legitimate.  */
@@ -5835,7 +5358,7 @@ static bool
 h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
 {
   return (TYPE_MODE (type) == BLKmode
-	  || GET_MODE_SIZE (TYPE_MODE (type)) > (TARGET_H8300 ? 4 : 8));
+	  || GET_MODE_SIZE (TYPE_MODE (type)) > 8);
 }
 
 /* We emit the entire trampoline here.  Depending on the pointer size,
diff --git a/gcc/config/h8300/h8300.h b/gcc/config/h8300/h8300.h
index 50dd7e7..bf20ce2 100644
--- a/gcc/config/h8300/h8300.h
+++ b/gcc/config/h8300/h8300.h
@@ -23,11 +23,6 @@ along with GCC; see the file COPYING3.  If not see
 #ifndef GCC_H8300_H
 #define GCC_H8300_H
 
-/* Which CPU to compile for.
-   We use int for CPU_TYPE to avoid lots of casts.  */
-#if 0 /* defined in insn-attr.h, here for documentation */
-enum attr_cpu { CPU_H8300, CPU_H8300H };
-#endif
 extern int cpu_type;
 
 /* Various globals defined in h8300.c.  */
@@ -57,7 +52,7 @@ extern const char * const *h8_reg_names;
 	      builtin_define ("__NORMAL_MODE__");	\
 	    }						\
 	}						\
-      else if (TARGET_H8300H)				\
+      else						\
 	{						\
 	  builtin_define ("__H8300H__");		\
 	  builtin_assert ("cpu=h8300h");		\
@@ -67,12 +62,6 @@ extern const char * const *h8_reg_names;
 	      builtin_define ("__NORMAL_MODE__");	\
 	    }						\
 	}						\
-      else						\
-	{						\
-	  builtin_define ("__H8300__");			\
-	  builtin_assert ("cpu=h8300");			\
-	  builtin_assert ("machine=h8300");		\
-	}						\
     }							\
   while (0)
 
@@ -81,7 +70,6 @@ extern const char * const *h8_reg_names;
 /* Macros used in the machine description to test the flags.  */
 
 /* Select between the H8/300 and H8/300H CPUs.  */
-#define TARGET_H8300	(! TARGET_H8300H && ! TARGET_H8300S)
 #define TARGET_H8300S	(TARGET_H8300S_1 || TARGET_H8300SX)
 /* Some multiply instructions are not available in all H8SX variants.
    Use this macro instead of TARGET_H8300SX to indicate this, even
@@ -114,7 +102,7 @@ extern const char * const *h8_reg_names;
 /* Default target_flags if no switches specified.  */
 
 #ifndef TARGET_DEFAULT
-#define TARGET_DEFAULT (MASK_QUICKCALL)
+#define TARGET_DEFAULT (MASK_H8300H | MASK_QUICKCALL)
 #endif
 
 /* We want dwarf2 info available to gdb.  */
@@ -154,7 +142,7 @@ extern const char * const *h8_reg_names;
 #define MAX_BITS_PER_WORD	32
 
 /* Width of a word, in units (bytes).  */
-#define UNITS_PER_WORD		(TARGET_H8300H || TARGET_H8300S ? 4 : 2)
+#define UNITS_PER_WORD		4
 #define MIN_UNITS_PER_WORD	2
 
 #define SHORT_TYPE_SIZE	16
@@ -168,7 +156,7 @@ extern const char * const *h8_reg_names;
 #define MAX_FIXED_MODE_SIZE	32
 
 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
-#define PARM_BOUNDARY (TARGET_H8300H || TARGET_H8300S ? 32 : 16)
+#define PARM_BOUNDARY 32
 
 /* Allocation boundary (in *bits*) for the code of a function.  */
 #define FUNCTION_BOUNDARY 16
@@ -182,10 +170,10 @@ extern const char * const *h8_reg_names;
 /* No data type wants to be aligned rounder than this.
    32-bit values are aligned as such on the H8/300H and H8S for speed.  */
 #define BIGGEST_ALIGNMENT \
-(((TARGET_H8300H || TARGET_H8300S) && ! TARGET_ALIGN_300) ? 32 : 16)
+((! TARGET_ALIGN_300) ? 32 : 16)
 
-/* The stack goes in 16/32 bit lumps.  */
-#define STACK_BOUNDARY (TARGET_H8300 ? 16 : 32)
+/* The stack goes in 32 bit lumps.  */
+#define STACK_BOUNDARY 32
 
 /* Define this if move instructions will actually fail to work
    when given unaligned data.  */
@@ -478,8 +466,8 @@ struct cum_arg
   (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF	\
    || (GET_CODE (X) == CONST_INT				\
        /* We handle signed and unsigned offsets here.  */	\
-       && INTVAL (X) > (TARGET_H8300 ? -0x10000 : -0x1000000)	\
-       && INTVAL (X) < (TARGET_H8300 ? 0x10000 : 0x1000000))	\
+       && INTVAL (X) > -0x1000000				\
+       && INTVAL (X) < 0x1000000)				\
    || (GET_CODE (X) == HIGH || GET_CODE (X) == CONST))
 
 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
@@ -530,7 +518,7 @@ struct cum_arg
 
 /* Max number of bytes we can move from memory to memory
    in one reasonably fast instruction.  */
-#define MOVE_MAX	(TARGET_H8300H || TARGET_H8300S ? 4 : 2)
+#define MOVE_MAX	4
 #define MAX_MOVE_MAX	4
 
 /* Nonzero if access to memory by bytes is slow and undesirable.  */
@@ -545,18 +533,18 @@ struct cum_arg
    After generation of rtl, the compiler makes no further distinction
    between pointers and any other objects of this machine mode.  */
 #define Pmode								      \
-  ((TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE ? SImode : HImode)
+  (!TARGET_NORMAL_MODE ? SImode : HImode)
 
 /* ANSI C types.
    We use longs for the H8/300H and the H8S because ints can be 16 or 32.
    GCC requires SIZE_TYPE to be the same size as pointers.  */
 #define SIZE_TYPE								\
-  (TARGET_H8300 || TARGET_NORMAL_MODE ? TARGET_INT32 ? "short unsigned int" : "unsigned int" : "long unsigned int")
+  (TARGET_NORMAL_MODE ? TARGET_INT32 ? "short unsigned int" : "unsigned int" : "long unsigned int")
 #define PTRDIFF_TYPE						\
-  (TARGET_H8300 || TARGET_NORMAL_MODE ? TARGET_INT32 ? "short int" : "int" : "long int")
+  (TARGET_NORMAL_MODE ? TARGET_INT32 ? "short int" : "int" : "long int")
 
 #define POINTER_SIZE							\
-  ((TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE ? 32 : 16)
+  (!TARGET_NORMAL_MODE ? 32 : 16)
 
 #define WCHAR_TYPE "short unsigned int"
 #define WCHAR_TYPE_SIZE 16
@@ -611,7 +599,7 @@ struct cum_arg
 
 /* The assembler op to get a word, 2 bytes for the H8/300, 4 for H8/300H.  */
 #define ASM_WORD_OP							\
-  (TARGET_H8300 || TARGET_NORMAL_MODE ? "\t.word\t" : "\t.long\t")
+  (TARGET_NORMAL_MODE ? "\t.word\t" : "\t.long\t")
 
 #define TEXT_SECTION_ASM_OP "\t.section .text"
 #define DATA_SECTION_ASM_OP "\t.section .data"
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index a86b8ea..f87b0f7 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -167,8 +167,7 @@
 
 (define_asm_attributes
   [(set (attr "length")
-	(cond [(match_test "TARGET_H8300") (const_int 4)
-	       (match_test "TARGET_H8300H") (const_int 10)
+	(cond [(match_test "TARGET_H8300H") (const_int 10)
 	       (match_test "TARGET_H8300S") (const_int 10)]
 	      (const_int 14)))])
 
@@ -205,7 +204,7 @@
 (define_insn "*movqi_h8nosx"
   [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
 	(match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
-  "(TARGET_H8300 || TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
+  "!TARGET_H8300SX
     && h8300_move_ok (operands[0], operands[1])"
   "@
    sub.b	%X0,%X0
@@ -234,13 +233,7 @@
   ""
   {
     enum machine_mode mode = <MODE>mode;
-    if (TARGET_H8300 && (mode == SImode || mode == SFmode))
-      {
-	/* The original H8/300 needs to split up 32 bit moves.  */
-	if (h8300_expand_movsi (operands))
-	  DONE;
-      }
-    else if (!TARGET_H8300SX)
+    if (!TARGET_H8300SX)
       {
 	/* Other H8 chips, except the H8/SX family can only handle a
 	   single memory operand, which is checked by h8300_move_ok.
@@ -268,7 +261,7 @@
 (define_insn "*movhi_h8nosx"
   [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
 	(match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
-  "(TARGET_H8300 || TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
+  "!TARGET_H8300SX
     && h8300_move_ok (operands[0], operands[1])"
   "@
    sub.w	%T0,%T0
@@ -308,76 +301,6 @@
    (set_attr "cc" "set_zn,set_znv,set_znv")])
 
 ;; movsi
-
-(define_insn "*movsi_h8300"
-  [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
-	(match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
-  "TARGET_H8300
-   && h8300_move_ok (operands[0], operands[1])"
-{
-  unsigned int rn = -1;
-  switch (which_alternative)
-    {
-    case 0:
-      return "sub.w	%e0,%e0\;sub.w	%f0,%f0";
-    case 1:
-      if (REGNO (operands[0]) < REGNO (operands[1]))
-	return "mov.w	%e1,%e0\;mov.w	%f1,%f0";
-      else
-	return "mov.w	%f1,%f0\;mov.w	%e1,%e0";
-    case 2:
-      /* Make sure we don't trample the register we index with.  */
-      if (GET_CODE (operands[1]) == MEM)
-	{
-	  rtx inside = XEXP (operands[1], 0);
-	  if (REG_P (inside))
-	    {
-	      rn = REGNO (inside);
-	    }
-	  else if (GET_CODE (inside) == PLUS)
-	    {
-	      rtx lhs = XEXP (inside, 0);
-	      rtx rhs = XEXP (inside, 1);
-	      if (REG_P (lhs)) rn = REGNO (lhs);
-	      if (REG_P (rhs)) rn = REGNO (rhs);
-	    }
-	}
-      if (rn == REGNO (operands[0]))
-	{
-	  /* Move the second word first.  */
-	  return "mov.w	%f1,%f0\;mov.w	%e1,%e0";
-	}
-      else
-	{
-	  if (GET_CODE (operands[1]) == CONST_INT)
-	    {
-	      /* If either half is zero, use sub.w to clear that
-		 half.  */
-	      if ((INTVAL (operands[1]) & 0xffff) == 0)
-		return "mov.w	%e1,%e0\;sub.w	%f0,%f0";
-	      if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
-		return "sub.w	%e0,%e0\;mov.w	%f1,%f0";
-	      /* If the upper half and the lower half are the same,
-		 copy one half to the other.  */
-	      if ((INTVAL (operands[1]) & 0xffff)
-		  == ((INTVAL (operands[1]) >> 16) & 0xffff))
-		return "mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0";
-	    }
-	  return "mov.w	%e1,%e0\;mov.w	%f1,%f0";
-	}
-    case 3:
-      return "mov.w	%e1,%e0\;mov.w	%f1,%f0";
-    case 4:
-      return "mov.w	%f1,%T0\;mov.w	%e1,%T0";
-    case 5:
-      return "mov.w	%T1,%e0\;mov.w	%T1,%f0";
-    default:
-      gcc_unreachable ();
-    }
-}
-  [(set (attr "length")
-	(symbol_ref "compute_mov_length (operands)"))])
-
 (define_insn "*movsi_h8300hs"
   [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
 	(match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
@@ -476,65 +399,10 @@
 
 (include "mova.md")
 
-(define_insn "*movsf_h8300"
-  [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
-	(match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
-  "TARGET_H8300
-   && (register_operand (operands[0], SFmode)
-       || register_operand (operands[1], SFmode))"
-{
-  /* Copy of the movsi stuff.  */
-  unsigned int rn = -1;
-  switch (which_alternative)
-    {
-    case 0:
-      return "sub.w	%e0,%e0\;sub.w	%f0,%f0";
-    case 1:
-      if (REGNO (operands[0]) < REGNO (operands[1]))
-	return "mov.w	%e1,%e0\;mov.w	%f1,%f0";
-      else
-	return "mov.w	%f1,%f0\;mov.w	%e1,%e0";
-    case 2:
-      /* Make sure we don't trample the register we index with.  */
-      if (GET_CODE (operands[1]) == MEM)
-	{
-	  rtx inside = XEXP (operands[1], 0);
-	  if (REG_P (inside))
-	    {
-	      rn = REGNO (inside);
-	    }
-	  else if (GET_CODE (inside) == PLUS)
-	    {
-	      rtx lhs = XEXP (inside, 0);
-	      rtx rhs = XEXP (inside, 1);
-	      if (REG_P (lhs)) rn = REGNO (lhs);
-	      if (REG_P (rhs)) rn = REGNO (rhs);
-	    }
-	}
-      if (rn == REGNO (operands[0]))
-	/* Move the second word first.  */
-	return "mov.w	%f1,%f0\;mov.w	%e1,%e0";
-      else
-	/* Move the first word first.  */
-	return "mov.w	%e1,%e0\;mov.w	%f1,%f0";
-
-    case 3:
-      return "mov.w	%e1,%e0\;mov.w	%f1,%f0";
-    case 4:
-      return "mov.w	%f1,%T0\;mov.w	%e1,%T0";
-    case 5:
-      return "mov.w	%T1,%e0\;mov.w	%T1,%f0";
-    default:
-      gcc_unreachable ();
-    }
-}
-  [(set (attr "length")
-	(symbol_ref "compute_mov_length (operands)"))])
-
 (define_insn "*movsf_h8300hs"
   [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
 	(match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
-  "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
+  "!TARGET_H8300SX
     && (register_operand (operands[0], SFmode)
 	|| register_operand (operands[1], SFmode))"
   "@
@@ -552,23 +420,13 @@
 ;; PUSH INSTRUCTIONS
 ;; ----------------------------------------------------------------------
 
-(define_insn "*pushqi1_h8300"
-  [(set (mem:QI
-	(pre_modify:HI
-	  (reg:HI SP_REG)
-	  (plus:HI (reg:HI SP_REG) (const_int -2))))
-	(match_operand:QI 0 "register_no_sp_elim_operand" "r"))]
-  "TARGET_H8300"
-  "mov.w\\t%T0,@-r7"
-  [(set_attr "length" "2")])
-
 (define_insn "*push1_h8300hs_<QHI:mode>"
   [(set (mem:QHI
 	(pre_modify:P
 	  (reg:P SP_REG)
 	  (plus:P (reg:P SP_REG) (const_int -4))))
 	(match_operand:QHI 0 "register_no_sp_elim_operand" "r"))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "mov.l\\t%S0,@-er7"
   [(set_attr "length" "4")])
 
@@ -577,17 +435,6 @@
 ;; TEST INSTRUCTIONS
 ;; ----------------------------------------------------------------------
 
-(define_insn ""
-  [(set (cc0)
-	(compare (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "r,U")
-				  (const_int 1)
-				  (match_operand 1 "const_int_operand" "n,n"))
-		 (const_int 0)))]
-  "TARGET_H8300"
-  "btst	%Z1,%Y0"
-  [(set_attr "length" "2,4")
-   (set_attr "cc" "set_zn,set_zn")])
-
 (define_insn_and_split "*tst_extzv_1_n"
   [(set (cc0)
 	(compare (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
@@ -595,7 +442,7 @@
 				  (match_operand 1 "const_int_operand" "n,n,n"))
 		 (const_int 0)))
    (clobber (match_scratch:QI 2 "=X,X,&r"))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "@
    btst\\t%Z1,%Y0
    btst\\t%Z1,%Y0
@@ -619,8 +466,7 @@
 				   (const_int 1)
 				   (match_operand 1 "const_int_operand" "n"))
 		 (const_int 0)))]
-  "(TARGET_H8300 || TARGET_H8300H || TARGET_H8300S)
-    && INTVAL (operands[1]) <= 15"
+  "INTVAL (operands[1]) <= 15"
   "btst	%Z1,%Y0"
   [(set_attr "length" "2")
    (set_attr "cc" "set_zn")])
@@ -632,8 +478,7 @@
 				  (match_operand 1 "const_int_operand" "n"))
 		 (const_int 0)))
    (clobber (match_scratch:SI 2 "=&r"))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && INTVAL (operands[1]) >= 16"
+  "INTVAL (operands[1]) >= 16"
   "#"
   "&& reload_completed"
   [(set (match_dup 2)
@@ -657,7 +502,7 @@
 				  (and:SI (match_operand:SI 1 "register_operand" "r")
 					  (const_int 7)))
 		 (const_int 0)))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "btst	%w1,%w0"
   [(set_attr "length" "2")
    (set_attr "cc" "set_zn")])
@@ -670,7 +515,7 @@
 					  (const_int 7)))
 		 (const_int 0)))
    (clobber (match_scratch:QI 2 "=X,X,&r"))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "@
    btst\\t%w1,%X0
    btst\\t%w1,%X0
@@ -719,7 +564,7 @@
   [(set (cc0)
 	(compare (match_operand:SI 0 "register_operand" "r")
 		 (const_int 0)))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "mov.l	%S0,%S0"
   [(set_attr "length" "2")
    (set_attr "cc" "set_znv")])
@@ -743,20 +588,11 @@
   [(set_attr "length_table" "add")
    (set_attr "cc" "compare")])
 
-(define_insn "*cmphi_h8300_znvc"
-  [(set (cc0)
-	(compare (match_operand:HI 0 "register_operand" "r")
-		 (match_operand:HI 1 "register_operand" "r")))]
-  "TARGET_H8300"
-  "cmp.w	%T1,%T0"
-  [(set_attr "length" "2")
-   (set_attr "cc" "compare")])
-
 (define_insn "*cmphi_h8300hs_znvc"
   [(set (cc0)
 	(compare (match_operand:HI 0 "h8300_dst_operand" "rU,rQ")
 		 (match_operand:HI 1 "h8300_src_operand" "P3>X,rQi")))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
 {
   switch (which_alternative)
     {
@@ -778,7 +614,7 @@
   [(set (cc0)
 	(compare (match_operand:SI 0 "h8300_dst_operand" "r,rQ")
 		 (match_operand:SI 1 "h8300_src_operand" "P3>X,rQi")))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
 {
   switch (which_alternative)
     {
@@ -817,57 +653,11 @@
   [(set_attr "length_table" "add")
    (set_attr "cc" "set_zn")])
 
-(define_insn "*addhi3_h8300"
-  [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
-	(plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
-		 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
-  "TARGET_H8300"
-  "@
-   adds	%2,%T0
-   subs	%G2,%T0
-   add.b	%t2,%t0
-   add.b	%s2,%s0\;addx	%t2,%t0
-   add.w	%T2,%T0"
-  [(set_attr "length" "2,2,2,4,2")
-   (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
-
-;; This splitter is very important to make the stack adjustment
-;; interrupt-safe.  The combination of add.b and addx is unsafe!
-;;
-;; We apply this split after the peephole2 pass so that we won't end
-;; up creating too many adds/subs when a scratch register is
-;; available, which is actually a common case because stack unrolling
-;; tends to happen immediately after a function call.
-
-(define_split
-  [(set (match_operand:HI 0 "stack_pointer_operand" "")
-	(plus:HI (match_dup 0)
-		 (match_operand 1 "const_int_gt_2_operand" "")))]
-  "TARGET_H8300 && epilogue_completed"
-  [(const_int 0)]
-  {
-    split_adds_subs (HImode, operands);
-    DONE;
-  })
-
-(define_peephole2
-  [(match_scratch:HI 2 "r")
-   (set (match_operand:HI 0 "stack_pointer_operand" "")
-	(plus:HI (match_dup 0)
-		 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
-  "TARGET_H8300"
-  [(set (match_dup 2)
-	(match_dup 1))
-   (set (match_dup 0)
-	(plus:HI (match_dup 0)
-		 (match_dup 2)))]
-  "")
-
 (define_insn "*addhi3_h8300hs"
   [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
 	(plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
 		 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
-  "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
+  "!TARGET_H8300SX"
   "@
    adds	%2,%S0
    subs	%G2,%S0
@@ -882,7 +672,7 @@
 	(unspec:HSI [(match_operand:HSI 1 "register_operand" "0,0")
 		     (match_operand:HSI 2 "incdec_operand" "M,O")]
 		    UNSPEC_INCDEC))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   {
     if (which_alternative == 0)
       return <MODE>mode == HImode ? "inc.w\t%2,%T0" : "inc.l\t%2,%S0";
@@ -919,24 +709,11 @@
   })
 
 
-(define_insn "*addsi_h8300"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(plus:SI (match_operand:SI 1 "register_operand" "%0,0")
-		 (match_operand:SI 2 "h8300_src_operand" "n,r")))]
-  "TARGET_H8300"
-{
-  return output_plussi (operands);
-}
-  [(set (attr "length")
-	(symbol_ref "compute_plussi_length (operands)"))
-   (set (attr "cc")
-	(symbol_ref "compute_plussi_cc (operands)"))])
-
 (define_insn "*addsi_h8300hs"
   [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
 	(plus:SI (match_operand:SI 1 "h8300_dst_operand" "%0,0")
 		 (match_operand:SI 2 "h8300_src_operand" "i,rQ")))]
-  "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
+  "h8300_operands_match_p (operands)"
 {
   return output_plussi (operands);
 }
@@ -949,7 +726,7 @@
   [(set (match_operand:SI 0 "register_operand" "")
 	(plus:SI (match_dup 0)
 		 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   [(const_int 0)]
   {
     split_adds_subs (SImode, operands);
@@ -966,8 +743,6 @@
 		    (match_operand:QHSI 2 "h8300_src_operand" "")))]
   ""
   {
-    if (TARGET_H8300 && <MODE>mode == SImode)
-      operands[2] = force_reg (SImode, operands[2]);
   })
 
 (define_insn "*subqi3"
@@ -979,22 +754,11 @@
   [(set_attr "length_table" "add")
    (set_attr "cc" "set_zn")])
 
-(define_insn "*subhi3_h8300"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(minus:HI (match_operand:HI 1 "register_operand" "0,0")
-		  (match_operand:HI 2 "h8300_src_operand" "r,n")))]
-  "TARGET_H8300"
-  "@
-   sub.w	%T2,%T0
-   add.b	%E2,%s0\;addx	%F2,%t0"
-  [(set_attr "length" "2,4")
-   (set_attr "cc" "set_zn,clobber")])
-
 (define_insn "*sub<mode>3_h8300hs"
   [(set (match_operand:HSI 0 "h8300_dst_operand" "=rQ,rQ")
 	(minus:HSI (match_operand:HSI 1 "h8300_dst_operand" "0,0")
 		   (match_operand:HSI 2 "h8300_src_operand" "rQ,i")))]
-  "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
+  "h8300_operands_match_p (operands)"
   { 
     if (<MODE>mode == HImode)
       return "sub.w	%T2,%T0";
@@ -1005,14 +769,6 @@
   [(set_attr "length_table" "add")
    (set_attr "cc" "set_zn")])
 
-(define_insn "*subsi3_h8300"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(minus:SI (match_operand:SI 1 "register_operand" "0")
-		  (match_operand:SI 2 "register_operand" "r")))]
-  "TARGET_H8300"
-  "sub.w	%f2,%f0\;subx	%y2,%y0\;subx	%z2,%z0"
-  [(set_attr "length" "6")])
-
 
 ;; ----------------------------------------------------------------------
 ;; MULTIPLY INSTRUCTIONS
@@ -1025,7 +781,7 @@
 	(mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" ""))
 		 ;; intentionally-mismatched modes
 		 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   {
     if (GET_MODE (operands[2]) != VOIDmode)
       operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]);
@@ -1044,7 +800,7 @@
   [(set (match_operand:HI 0 "register_operand" "=r")
 	(mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
 		 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "mulxs.b	%X2,%T0"
   [(set_attr "length" "4")
    (set_attr "cc" "set_zn")])
@@ -1054,7 +810,7 @@
 	(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
 		 ;; intentionally-mismatched modes
 		 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   {
     if (GET_MODE (operands[2]) != VOIDmode)
       operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]);
@@ -1073,7 +829,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
 		 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "mulxs.w	%T2,%S0"
   [(set_attr "length" "4")
    (set_attr "cc" "set_zn")])
@@ -1083,7 +839,7 @@
 	(mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" ""))
 		 ;; intentionally-mismatched modes
 		 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   {
     if (GET_MODE (operands[2]) != VOIDmode)
       operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]);
@@ -1112,7 +868,7 @@
 	(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
 		 ;; intentionally-mismatched modes
 		 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   {
     if (GET_MODE (operands[2]) != VOIDmode)
       operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]);
@@ -1131,7 +887,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
 		 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "mulxu.w	%T2,%S0"
   [(set_attr "length" "2")
    (set_attr "cc" "none_0hit")])
@@ -1259,7 +1015,7 @@
 	  (mod:HI
 	    (match_dup 1)
 	    (sign_extend:HI (match_dup 2)))))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
 {
   if (find_reg_note (insn, REG_UNUSED, operands[3]))
     return "divxs.b\\t%X2,%T0";
@@ -1279,7 +1035,7 @@
 	  (umod:SI
 	    (match_dup 1)
 	    (zero_extend:SI (match_dup 2)))))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
 {
   if (find_reg_note (insn, REG_UNUSED, operands[3]))
     return "divxu.w\\t%T2,%S0";
@@ -1299,7 +1055,7 @@
 	  (mod:SI
 	    (match_dup 1)
 	    (sign_extend:SI (match_dup 2)))))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
 {
   if (find_reg_note (insn, REG_UNUSED, operands[3]))
     return "divxs.w\\t%T2,%S0";
@@ -1460,7 +1216,7 @@
    || single_one_operand (operands[2], QImode)"
   {
     if (which_alternative == 0)
-      return <CODE> == IOR ? "bset\\t%V2,%R0" : "bnot\\t%V2,%R0"; 
+      return <CODE> == IOR ? "bset\\t%V2,%R0" : "bnot\\t%V2,%R0";
     else if (which_alternative == 1)
       return <CODE> == IOR ? "or\\t%X2,%X0" : "xor\\t%X2,%X0";
     gcc_unreachable ();
@@ -1500,24 +1256,7 @@
   [(set (match_operand:QHSIF 0 "register_operand" "")
 	(neg:QHSIF (match_operand:QHSIF 1 "register_operand" "")))]
   ""
-  {
-    enum machine_mode mode = <MODE>mode;
-    if (TARGET_H8300)
-      {
-	if (mode == QImode || mode == SFmode)
-	  ;
-	else if (mode == HImode)
-	  {
-	    emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
-	    DONE;
-	  }
-	else if (mode == SImode)
-	  {
-	    emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
-	    DONE;
-	  }
-      }
-  })
+  { })
 
 (define_insn "*negqi2"
   [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
@@ -1541,7 +1280,7 @@
 (define_insn "*neghi2_h8300hs"
   [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
 	(neg:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
-  "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
+  "h8300_operands_match_p (operands)"
   "neg.w	%T0"
   [(set_attr "length_table" "unary")
    (set_attr "cc" "set_zn")])
@@ -1549,24 +1288,18 @@
 (define_insn "*negsi2_h8300hs"
   [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
 	(neg:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
-  "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
+  "h8300_operands_match_p (operands)"
   "neg.l	%S0"
   [(set_attr "length_table" "unary")
    (set_attr "cc" "set_zn")])
 
-(define_insn "*negsf2_h8300"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(neg:SF (match_operand:SF 1 "register_operand" "0")))]
-  "TARGET_H8300"
-  "xor.b\\t#128,%z0"
-  [(set_attr "length" "2")])
-
 (define_insn "*negsf2_h8300hs"
   [(set (match_operand:SF 0 "register_operand" "=r")
-	(neg:SF (match_operand:SF 1 "register_operand" "0")))]
+       (neg:SF (match_operand:SF 1 "register_operand" "0")))]
   "TARGET_H8300H || TARGET_H8300S"
   "xor.w\\t#32768,%e0"
   [(set_attr "length" "4")])
+
 
 ;; ----------------------------------------------------------------------
 ;; ABSOLUTE VALUE INSTRUCTIONS
@@ -1578,17 +1311,10 @@
   ""
   "")
 
-(define_insn "*abssf2_h8300"
-  [(set (match_operand:SF 0 "register_operand" "=r")
-	(abs:SF (match_operand:SF 1 "register_operand" "0")))]
-  "TARGET_H8300"
-  "and.b\\t#127,%z0"
-  [(set_attr "length" "2")])
-
 (define_insn "*abssf2_h8300hs"
   [(set (match_operand:SF 0 "register_operand" "=r")
 	(abs:SF (match_operand:SF 1 "register_operand" "0")))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "and.w\\t#32767,%e0"
   [(set_attr "length" "4")])
 
@@ -1610,32 +1336,18 @@
   [(set_attr "length_table" "unary")
    (set_attr "cc" "set_znv")])
 
-(define_insn "*one_cmplhi2_h8300"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(not:HI (match_operand:HI 1 "register_operand" "0")))]
-  "TARGET_H8300"
-  "not	%s0\;not	%t0"
-  [(set_attr "length" "4")])
-
 (define_insn "*one_cmplhi2_h8300hs"
   [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
 	(not:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
-  "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
+  "h8300_operands_match_p (operands)"
   "not.w	%T0"
   [(set_attr "cc" "set_znv")
    (set_attr "length_table" "unary")])
 
-(define_insn "*one_cmplsi2_h8300"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(not:SI (match_operand:SI 1 "register_operand" "0")))]
-  "TARGET_H8300"
-  "not	%w0\;not	%x0\;not	%y0\;not	%z0"
-  [(set_attr "length" "8")])
-
 (define_insn "*one_cmplsi2_h8300hs"
   [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
 	(not:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
-  "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
+  "h8300_operands_match_p (operands)"
   "not.l	%S0"
   [(set_attr "cc" "set_znv")
    (set_attr "length_table" "unary")])
@@ -1664,11 +1376,6 @@
    (use (match_operand 3 ""))]
   ""
   {
-    /* Force operand1 into a register if we're compiling
-       for the H8/300.  */
-    if ((GET_CODE (operands[2]) != REG && operands[2] != const0_rtx)
-	&& TARGET_H8300)
-      operands[2] = force_reg (HImode, operands[2]);
     h8300_expand_branch (operands);
     DONE;
   })
@@ -1678,7 +1385,7 @@
          [(match_operand:SI 1 "h8300_dst_operand" "")
           (match_operand:SI 2 "h8300_src_operand" "")]))
    (use (match_operand 3 ""))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   {
     h8300_expand_branch (operands);
     DONE;
@@ -1843,18 +1550,10 @@
   ""
   "")
 
-(define_insn "*tablejump_h8300"
-  [(set (pc) (match_operand:HI 0 "register_operand" "r"))
-   (use (label_ref (match_operand 1 "" "")))]
-  "TARGET_H8300"
-  "jmp	@%0"
-  [(set_attr "cc" "none")
-   (set_attr "length" "2")])
-
 (define_insn "*tablejump_h8300hs_advanced"
   [(set (pc) (match_operand:SI 0 "register_operand" "r"))
    (use (label_ref (match_operand 1 "" "")))]
-  "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
+  "!TARGET_NORMAL_MODE"
   "jmp	@%0"
   [(set_attr "cc" "none")
    (set_attr "length" "2")])
@@ -1862,7 +1561,7 @@
 (define_insn "*tablejump_h8300hs_normal"
   [(set (pc) (match_operand:HI 0 "register_operand" "r"))
    (use (label_ref (match_operand 1 "" "")))]
-  "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
+  "TARGET_NORMAL_MODE"
   "jmp @%S0"
   [(set_attr "cc" "none")
    (set_attr "length" "2")])
@@ -1874,23 +1573,16 @@
   ""
   "")
 
-(define_insn "*indirect_jump_h8300"
-  [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
-  "TARGET_H8300"
-  "jmp	@%0"
-  [(set_attr "cc" "none")
-   (set_attr "length" "2")])
-
 (define_insn "*indirect_jump_h8300hs_advanced"
   [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
-  "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
+  "!TARGET_NORMAL_MODE"
   "jmp @%0"
   [(set_attr "cc" "none")
    (set_attr "length" "2")])
 
 (define_insn "*indirect_jump_h8300hs_normal"
   [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
-  "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
+  "TARGET_NORMAL_MODE"
   "jmp @%S0"
   [(set_attr "cc" "none")
    (set_attr "length" "2")])
@@ -1980,12 +1672,6 @@
 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
 ;; ----------------------------------------------------------------------
 
-(define_expand "push_h8300"
-  [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
-        (match_operand:HI 0 "register_operand" ""))]
-  "TARGET_H8300"
-  "")
-
 (define_expand "push_h8300hs_advanced"
   [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
         (match_operand:SI 0 "register_operand" ""))]
@@ -1998,12 +1684,6 @@
   "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
   "")
 
-(define_expand "pop_h8300"
-  [(set (match_operand:HI 0 "register_operand" "")
-	(mem:HI (post_inc:HI (reg:HI SP_REG))))]
-  "TARGET_H8300"
-  "")
-
 (define_expand "pop_h8300hs_advanced"
   [(set (match_operand:SI 0 "register_operand" "")
 	(mem:SI (post_inc:SI (reg:SI SP_REG))))]
@@ -2100,9 +1780,7 @@
   [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
   ""
 {
-  if (TARGET_H8300)
-    return "subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr";
-  else if (TARGET_H8300H && TARGET_NORMAL_MODE)
+  if (TARGET_H8300H && TARGET_NORMAL_MODE)
     return "subs\\t#2,er7\;mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr";
   else if (TARGET_H8300H)
     return "mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr";
@@ -2131,19 +1809,10 @@
       operands[1] = force_reg (QImode, operands[1]);
   })
 
-(define_insn "*zero_extendqihi2_h8300"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
-  "TARGET_H8300"
-  "@
-  mov.b	#0,%t0
-  #"
-  [(set_attr "length" "2,10")])
-
 (define_insn "*zero_extendqihi2_h8300hs"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
 	(zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "@
   extu.w	%T0
   #"
@@ -2167,26 +1836,16 @@
     operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));
   })
 
-
-(define_insn "*zero_extendqisi2_h8300"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
-  "TARGET_H8300"
-  "@
-  mov.b	#0,%x0\;sub.w	%e0,%e0
-  mov.b	%R1,%w0\;mov.b	#0,%x0\;sub.w	%e0,%e0"
-  [(set_attr "length" "4,8")])
-
 (define_insn "*zero_extendqisi2_h8300hs"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
 	(zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
-  "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
+  "!TARGET_H8300SX"
   "#")
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
 	(zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
-  "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
+  "!TARGET_H8300SX
     && reg_overlap_mentioned_p (operands[0], operands[1])
     && reload_completed"
   [(set (match_dup 2)
@@ -2203,7 +1862,7 @@
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
 	(zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
-  "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
+  "!TARGET_H8300SX
     && !reg_overlap_mentioned_p (operands[0], operands[1])
     && reload_completed"
   [(set (match_dup 0)
@@ -2228,21 +1887,10 @@
   ""
   "")
 
-;; %e prints the high part of a CONST_INT, not the low part.  Arggh.
-(define_insn "*zero_extendhisi2_h8300"
-  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
-  "TARGET_H8300"
-  "@
-  sub.w	%e0,%e0
-  mov.w	%f1,%f0\;sub.w	%e0,%e0
-  mov.w	%e1,%f0\;sub.w	%e0,%e0"
-  [(set_attr "length" "2,4,6")])
-
 (define_insn "*zero_extendhisi2_h8300hs"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "extu.l	%S0"
   [(set_attr "length" "2")
    (set_attr "cc" "set_znv")])
@@ -2253,32 +1901,14 @@
   ""
   "")
 
-(define_insn "*extendqihi2_h8300"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
-  "TARGET_H8300"
-  "@
-  bld	#7,%s0\;subx	%t0,%t0
-  mov.b	%R1,%s0\;bld	#7,%s0\;subx	%t0,%t0"
-  [(set_attr "length" "4,8")])
-
 (define_insn "*extendqihi2_h8300hs"
   [(set (match_operand:HI 0 "register_operand" "=r")
 	(sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "exts.w	%T0"
   [(set_attr "length" "2")
    (set_attr "cc" "set_znv")])
 
-(define_insn "*extendqisi2_h8300"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
-  "TARGET_H8300"
-  "@
-  bld	#7,%w0\;subx	%x0,%x0\;subx	%y0,%y0\;subx	%z0,%z0
-  mov.b	%R1,%w0\;bld	#7,%w0\;subx	%x0,%x0\;subx	%y0,%y0\;subx	%z0,%z0"
-  [(set_attr "length" "8,12")])
-
 ;; The following pattern is needed because without the pattern, the
 ;; combiner would split (sign_extend:SI (reg:QI)) into two 24-bit
 ;; shifts, one ashift and one ashiftrt.
@@ -2286,7 +1916,7 @@
 (define_insn_and_split "*extendqisi2_h8300hs"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
-  "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
+  "!TARGET_H8300SX"
   "#"
   "&& reload_completed"
   [(set (match_dup 2)
@@ -2311,19 +1941,10 @@
   ""
   "")
 
-(define_insn "*extendhisi2_h8300"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
-  "TARGET_H8300"
-  "@
-  bld	#7,%x0\;subx	%y0,%y0\;subx	%z0,%z0
-  mov.w	%T1,%f0\;bld	#7,%x0\;subx	%y0,%y0\;subx	%z0,%z0"
-  [(set_attr "length" "6,10")])
-
 (define_insn "*extendhisi2_h8300hs"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "exts.l	%S0"
   [(set_attr "length" "2")
    (set_attr "cc" "set_znv")])
@@ -2654,7 +2275,7 @@
   [(set (match_operand:SI 0 "register_operand" "")
 	(rotate:SI (match_operand:SI 1 "register_operand" "")
 		   (match_operand:QI 2 "nonmemory_operand" "")))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   {
     if (expand_a_rotate (operands))
     DONE;
@@ -2664,7 +2285,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(rotate:SI (match_operand:SI 1 "register_operand" "0")
 		   (match_operand:QI 2 "immediate_operand" "")))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
 {
   return output_a_rotate (ROTATE, operands);
 }
@@ -2685,19 +2306,6 @@
 ;; canonicalize the form better.
 
 ;;
-;; Normal loads with a 16bit destination.
-;;
-
-(define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "=&r")
-	(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
-			 (const_int 1)
-			 (match_operand:HI 2 "immediate_operand" "n")))]
-  "TARGET_H8300"
-  "sub.w	%0,%0\;bld	%Z2,%Y1\;bst	#0,%X0"
-  [(set_attr "length" "6")])
-
-;;
 ;; Inverted loads with a 16bit destination.
 ;;
 
@@ -2707,7 +2315,7 @@
 				 (match_operand:HI 3 "const_int_operand" "n"))
 			 (const_int 1)
 			 (match_operand:HI 2 "const_int_operand" "n")))]
-  "(TARGET_H8300 || TARGET_H8300SX)
+  "(TARGET_H8300SX)
     && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
   "sub.w	%0,%0\;bild	%Z2,%Y1\;bst	#0,%X0"
   [(set_attr "length" "8")])
@@ -2716,23 +2324,12 @@
 ;; Normal loads with a 32bit destination.
 ;;
 
-(define_insn "*extzv_1_r_h8300"
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(zero_extract:SI (match_operand:HI 1 "register_operand" "r")
-			 (const_int 1)
-			 (match_operand 2 "const_int_operand" "n")))]
-  "TARGET_H8300 && INTVAL (operands[2]) < 16"
-{
-  return output_simode_bld (0, operands);
-}
-  [(set_attr "length" "8")])
-
 (define_insn "*extzv_1_r_h8300hs"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
 	(zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
 			 (const_int 1)
 			 (match_operand 2 "const_int_operand" "n,n")))]
-  "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16"
+  "INTVAL (operands[2]) < 16"
 {
   return output_simode_bld (0, operands);
 }
@@ -2743,26 +2340,13 @@
 ;; Inverted loads with a 32bit destination.
 ;;
 
-(define_insn "*extzv_1_r_inv_h8300"
-  [(set (match_operand:SI 0 "register_operand" "=&r")
-	(zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
-				 (match_operand:HI 3 "const_int_operand" "n"))
-			 (const_int 1)
-			 (match_operand 2 "const_int_operand" "n")))]
-  "TARGET_H8300 && INTVAL (operands[2]) < 16
-   && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
-{
-  return output_simode_bld (1, operands);
-}
-  [(set_attr "length" "8")])
-
 (define_insn "*extzv_1_r_inv_h8300hs"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
 	(zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
 				 (match_operand 3 "const_int_operand" "n,n"))
 			 (const_int 1)
 			 (match_operand 2 "const_int_operand" "n,n")))]
-  "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16
+  "INTVAL (operands[2]) < 16
     && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
 {
   return output_simode_bld (1, operands);
@@ -2775,61 +2359,46 @@
 			 (match_operand:HI 1 "general_operand" "")
 			 (match_operand:HI 2 "general_operand" ""))
 	(match_operand:HI 3 "general_operand" ""))]
-  "TARGET_H8300 || TARGET_H8300SX"
+  "TARGET_H8300SX"
   {
-    if (TARGET_H8300SX)
+    if (GET_CODE (operands[1]) == CONST_INT
+	&& GET_CODE (operands[2]) == CONST_INT
+	&& INTVAL (operands[1]) <= 8
+	&& INTVAL (operands[2]) >= 0
+	&& INTVAL (operands[1]) + INTVAL (operands[2]) <= 8
+	&& memory_operand (operands[0], GET_MODE (operands[0])))
       {
-	if (GET_CODE (operands[1]) == CONST_INT
-	    && GET_CODE (operands[2]) == CONST_INT
-	    && INTVAL (operands[1]) <= 8
-	    && INTVAL (operands[2]) >= 0
-	    && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8
-	    && memory_operand (operands[0], GET_MODE (operands[0])))
+	/* If the source operand is zero, it's better to use AND rather
+	   than BFST.  Likewise OR if the operand is all ones.  */
+	if (GET_CODE (operands[3]) == CONST_INT)
+	  {
+	    HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1;
+	    if ((INTVAL (operands[3]) & mask) == 0)
+	      FAIL;
+	    if ((INTVAL (operands[3]) & mask) == mask)
+	      FAIL;
+	  }
+	if (! bit_memory_operand (operands[0], GET_MODE (operands[0])))
+	  {
+	    if (!can_create_pseudo_p ())
+	      FAIL;
+	    operands[0] =  replace_equiv_address (operands[0], force_reg (Pmode,
+						  XEXP (operands[0], 0)));
+	  }
+	operands[3] = gen_lowpart (QImode, operands[3]);
+	if (! operands[3])
+	  FAIL;
+	if (! register_operand (operands[3], QImode))
 	  {
-	    /* If the source operand is zero, it's better to use AND rather
-	       than BFST.  Likewise OR if the operand is all ones.  */
-	    if (GET_CODE (operands[3]) == CONST_INT)
-	      {
-		HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1;
-		if ((INTVAL (operands[3]) & mask) == 0)
-		  FAIL;
-		if ((INTVAL (operands[3]) & mask) == mask)
-		  FAIL;
-	      }
-	    if (! bit_memory_operand (operands[0], GET_MODE (operands[0])))
-	      {
-		if (!can_create_pseudo_p ())
-		  FAIL;
-		operands[0] =  replace_equiv_address (operands[0], force_reg (Pmode,
-						      XEXP (operands[0], 0)));
-	      }
-	    operands[3] = gen_lowpart (QImode, operands[3]);
-	    if (! operands[3])
+	    if (!can_create_pseudo_p ())
 	      FAIL;
-	    if (! register_operand (operands[3], QImode))
-	      {
-		if (!can_create_pseudo_p ())
-		  FAIL;
-		operands[3] = force_reg (QImode, operands[3]);
-	      }
-	    emit_insn (gen_bfst (adjust_address (operands[0], QImode, 0),
-						 operands[3], operands[1], operands[2]));
-	    DONE;
+	    operands[3] = force_reg (QImode, operands[3]);
 	  }
-	FAIL;
+	emit_insn (gen_bfst (adjust_address (operands[0], QImode, 0),
+					     operands[3], operands[1], operands[2]));
+	DONE;
       }
-
-    /* We only have single bit bit-field instructions.  */
-    if (INTVAL (operands[1]) != 1)
-      FAIL;
-
-    /* For now, we don't allow memory operands.  */
-    if (GET_CODE (operands[0]) == MEM
-	|| GET_CODE (operands[3]) == MEM)
-      FAIL;
-
-    if (GET_CODE (operands[3]) != REG)
-      operands[3] = force_reg (HImode, operands[3]);
+    FAIL;
   })
 
 (define_insn ""
@@ -2846,56 +2415,45 @@
 	(zero_extract:HI (match_operand:HI 1 "bit_operand" "")
 			 (match_operand:HI 2 "general_operand" "")
 			 (match_operand:HI 3 "general_operand" "")))]
-  "TARGET_H8300 || TARGET_H8300SX"
+  "TARGET_H8300SX"
   {
-    if (TARGET_H8300SX)
+    if (GET_CODE (operands[2]) == CONST_INT
+	&& GET_CODE (operands[3]) == CONST_INT
+	&& INTVAL (operands[2]) <= 8
+	&& INTVAL (operands[3]) >= 0
+	&& INTVAL (operands[2]) + INTVAL (operands[3]) <= 8
+	&& memory_operand (operands[1], QImode))
       {
-	if (GET_CODE (operands[2]) == CONST_INT
-	    && GET_CODE (operands[3]) == CONST_INT
-	    && INTVAL (operands[2]) <= 8
-	    && INTVAL (operands[3]) >= 0
-	    && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8
-	    && memory_operand (operands[1], QImode))
+	rtx temp;
+
+	/* Optimize the case where we're extracting into a paradoxical
+	   subreg.  It's only necessary to extend to the inner reg.  */
+	if (GET_CODE (operands[0]) == SUBREG
+	    && subreg_lowpart_p (operands[0])
+	    && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
+		< GET_MODE_SIZE (GET_MODE (operands[0])))
+	    && (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0])))
+		== MODE_INT))
+	   operands[0] = SUBREG_REG (operands[0]);
+
+	if (!can_create_pseudo_p ())
+	  temp = gen_lowpart (QImode, operands[0]);
+	else
+	  temp = gen_reg_rtx (QImode);
+	if (! temp)
+	  FAIL;
+        if (! bit_memory_operand (operands[1], QImode))
 	  {
-	    rtx temp;
-
-	    /* Optimize the case where we're extracting into a paradoxical
-	       subreg.  It's only necessary to extend to the inner reg.  */
-	    if (GET_CODE (operands[0]) == SUBREG
-		&& subreg_lowpart_p (operands[0])
-		&& (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
-		    < GET_MODE_SIZE (GET_MODE (operands[0])))
-		&& (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0])))
-		    == MODE_INT))
-	      operands[0] = SUBREG_REG (operands[0]);
-
 	    if (!can_create_pseudo_p ())
-	      temp = gen_lowpart (QImode, operands[0]);
-	    else
-	      temp = gen_reg_rtx (QImode);
-	    if (! temp)
 	      FAIL;
-            if (! bit_memory_operand (operands[1], QImode))
-	      {
-		if (!can_create_pseudo_p ())
-		  FAIL;
-		operands[1] = replace_equiv_address (operands[1],
-						     force_reg (Pmode, XEXP (operands[1], 0)));
-	      }
-	    emit_insn (gen_bfld (temp, operands[1], operands[2], operands[3]));
-	    convert_move (operands[0], temp, 1);
-	    DONE;
-          }
-	FAIL;
+	    operands[1] = replace_equiv_address (operands[1],
+						 force_reg (Pmode, XEXP (operands[1], 0)));
+	  }
+	emit_insn (gen_bfld (temp, operands[1], operands[2], operands[3]));
+	convert_move (operands[0], temp, 1);
+	DONE;
       }
-
-    /* We only have single bit bit-field instructions.  */
-    if (INTVAL (operands[2]) != 1)
-      FAIL;
-
-    /* For now, we don't allow memory operands.  */
-    if (GET_CODE (operands[1]) == MEM)
-      FAIL;
+    FAIL;
   })
 
 ;; BAND, BOR, and BXOR patterns
@@ -3186,7 +2744,7 @@
 			 (const_int 1)
 			 (match_operand:SI 1 "const_int_operand" "n"))
 	(match_operand:SI 2 "register_operand" "r"))]
-  "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[1]) < 16"
+  "INTVAL (operands[1]) < 16"
   "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
   [(set_attr "length" "4")])
 
@@ -3196,9 +2754,7 @@
 			 (match_operand:SI 1 "const_int_operand" "n"))
 	(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
 		     (match_operand:SI 3 "const_int_operand" "n")))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && INTVAL (operands[1]) < 16
-    && INTVAL (operands[3]) < 16"
+  "INTVAL (operands[1]) < 16 && INTVAL (operands[3]) < 16"
   "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
   [(set_attr "length" "4")])
 
@@ -3208,7 +2764,7 @@
 			 (match_operand:SI 1 "const_int_operand" "n"))
 	(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
 		     (const_int 16)))]
-  "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[1]) < 16"
+  "INTVAL (operands[1]) < 16"
   "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
   [(set_attr "length" "6")])
 
@@ -3217,7 +2773,7 @@
 			 (const_int 8)
 			 (const_int 8))
 	(match_operand:SI 1 "register_operand" "r"))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "mov.b\\t%w1,%x0"
   [(set_attr "length" "2")])
 
@@ -3227,7 +2783,7 @@
 			 (const_int 8))
 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
 		     (const_int 8)))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "mov.b\\t%x1,%x0"
   [(set_attr "length" "2")])
 
@@ -3238,7 +2794,7 @@
 	(zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
 			 (const_int 8)
 			 (const_int 8)))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "@
    mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
    sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
@@ -3250,7 +2806,7 @@
 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
 			 (const_int 8)
 			 (const_int 16)))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
   [(set_attr "cc" "set_znv")
    (set_attr "length" "6")])
@@ -3273,7 +2829,7 @@
 	(zero_extract:SI (match_operand:SI 1 "register_operand" "0")
 			 (const_int 8)
 			 (const_int 23)))]
-  "(TARGET_H8300H || TARGET_H8300S)"
+  ""
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 0)
@@ -3295,7 +2851,7 @@
 	(and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
 			   (const_int 15))
 		(const_int 2147450880)))]
-  "(TARGET_H8300H || TARGET_H8300S)"
+  ""
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 0)
@@ -3316,10 +2872,9 @@
 			   (match_operand:QI 2 "const_int_operand" "S,n"))
 		(match_operand:SI 3 "const_int_operand" "n,n")))
    (clobber (match_scratch:QI 4 "=X,&r"))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && INTVAL (operands[2]) <= 15
-    && UINTVAL (operands[3]) == ((HOST_WIDE_INT_M1U << INTVAL (operands[2]))
-				 & 0xffff)"
+  "INTVAL (operands[2]) <= 15
+   && UINTVAL (operands[3]) == ((HOST_WIDE_INT_M1U << INTVAL (operands[2]))
+				& 0xffff)"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 5)
@@ -3339,9 +2894,8 @@
 	(and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
 			     (match_operand:SI 2 "const_int_operand" "n"))
 		(match_operand:SI 3 "single_one_operand" "n")))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && exact_log2 (INTVAL (operands[3])) < 16
-    && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
+  "exact_log2 (INTVAL (operands[3])) < 16
+   && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
 {
   operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
   return "shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0";
@@ -3353,7 +2907,7 @@
 	(and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
 			     (const_int 9))
 		(const_int 4194304)))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "#"
   "&& reload_completed"
   [(set (match_dup 0)
@@ -3373,7 +2927,7 @@
 	(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
 			  (const_int 65536))
 		 (match_operand:SI 2 "register_operand" "0")))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "add.w\\t%f1,%e0"
   [(set_attr "length" "2")])
 
@@ -3382,7 +2936,7 @@
 	(plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
 			      (const_int 16))
 		 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
   [(set_attr "length" "6")])
 
@@ -3391,7 +2945,7 @@
 	(plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
 			 (const_int 1))
 		 (match_operand:SI 2 "register_operand" "0")))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "#"
   "&& reload_completed"
   [(set (cc0) (compare (zero_extract:SI (match_dup 1)
@@ -3416,7 +2970,7 @@
 	(plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
 			 (const_int 1))
 		 (match_operand:SI 2 "register_operand" "0")))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "#"
   "&& reload_completed"
   [(set (cc0) (compare (zero_extract:SI (match_dup 1)
@@ -3463,7 +3017,7 @@
 	(match_operator:SI 1 "iorxor_operator"
 	 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
 	  (match_operand:SI 3 "register_operand" "0")]))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "%c1.w\\t%T2,%f0"
   [(set_attr "length" "2")])
 
@@ -3473,7 +3027,7 @@
 	 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
 		     (const_int 16))
 	  (match_operand:SI 3 "register_operand" "0")]))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "%c1.w\\t%f2,%e0"
   [(set_attr "length" "2")])
 
@@ -3483,7 +3037,7 @@
 	 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
 		       (const_int 16))
 	  (match_operand:SI 3 "register_operand" "0")]))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "%c1.w\\t%e2,%f0"
   [(set_attr "length" "2")])
 
@@ -3530,9 +3084,8 @@
 	(ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
 		(ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
 			   (const_int 8))))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && reload_completed
-    && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
+  "reload_completed
+   && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
   [(set (match_dup 0)
 	(match_dup 3))]
   {
@@ -3546,7 +3099,7 @@
 	(ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
 		(ashift:SI (match_operand:SI 2 "register_operand" "r")
 			   (const_int 16))))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "mov.w\\t%f2,%e0"
   [(set_attr "length" "2")])
 
@@ -3556,7 +3109,7 @@
 		(and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
 				   (const_int 8))
 			(const_int 65280))))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "#"
   "&& reload_completed"
   [(set (match_dup 3)
@@ -3575,7 +3128,7 @@
 			(const_int -65536))
 		(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
 			     (const_int 16))))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "mov.w\\t%e2,%f0"
   [(set_attr "length" "2")])
 
@@ -3584,7 +3137,7 @@
 	(ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
 		(ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
 			   (const_int 8))))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "#"
   "&& reload_completed"
   [(set (match_dup 3)
@@ -3603,7 +3156,7 @@
 	(ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
 			(const_int -256))
 		(zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "mov.b\\t%X2,%w0"
   [(set_attr "length" "2,8")])
 
@@ -3612,7 +3165,7 @@
 	(ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
 			   (const_int 31))
 		(match_operand:SI 2 "register_operand" "0")))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
   [(set_attr "length" "6")
    (set_attr "cc" "set_znv")])
@@ -3623,8 +3176,7 @@
 				   (match_operand:SI 2 "const_int_operand" "n"))
 			(match_operand:SI 3 "single_one_operand" "n"))
 		(match_operand:SI 4 "register_operand" "0")))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && (INTVAL (operands[3]) & ~0xffff) == 0"
+  "(INTVAL (operands[3]) & ~0xffff) == 0"
 {
   rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
 			- INTVAL (operands[2]));
@@ -3641,8 +3193,7 @@
 				     (match_operand:SI 2 "const_int_operand" "n"))
 			(match_operand:SI 3 "single_one_operand" "n"))
 		(match_operand:SI 4 "register_operand" "0")))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
+  "((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
 {
   rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
 			+ INTVAL (operands[2]));
@@ -3659,7 +3210,7 @@
 				 (const_int 1)
 				 (match_operand:SI 2 "const_int_operand" "n"))
 		(match_operand:SI 3 "register_operand" "0")))]
-  "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16"
+  "INTVAL (operands[2]) < 16"
   "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
   [(set_attr "length" "6")])
 
@@ -3669,7 +3220,7 @@
 				     (const_int 30))
 			(const_int 2))
 		(match_operand:SI 2 "register_operand" "0")))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
   [(set_attr "length" "8")])
 
@@ -3680,7 +3231,7 @@
 			(const_int 4194304))
 		(match_operand:SI 2 "register_operand" "0")))
    (clobber (match_scratch:HI 3 "=&r"))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
 {
   if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
     return "shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0";
@@ -3697,7 +3248,7 @@
 			   (const_int 23))
 		(match_operand:SI 2 "register_operand" "0")))
    (clobber (match_scratch:SI 3 "=&r"))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "#")
 
 (define_split
@@ -3706,10 +3257,9 @@
 			   (const_int 23))
 		(match_dup 0)))
    (clobber (match_operand:SI 2 "register_operand" ""))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && epilogue_completed
-    && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
-    && REGNO (operands[0]) != REGNO (operands[1])"
+  "epilogue_completed
+   && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
+   && REGNO (operands[0]) != REGNO (operands[1])"
   [(parallel [(set (match_dup 3)
 		   (ashift:HI (match_dup 3)
 			      (const_int 7)))
@@ -3728,10 +3278,9 @@
 			   (const_int 23))
 		(match_dup 0)))
    (clobber (match_operand:SI 2 "register_operand" ""))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && epilogue_completed
-    && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
-	 && REGNO (operands[0]) != REGNO (operands[1]))"
+  "epilogue_completed
+   && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
+	&& REGNO (operands[0]) != REGNO (operands[1]))"
   [(set (match_dup 2)
 	(match_dup 1))
    (parallel [(set (match_dup 3)
@@ -3752,7 +3301,7 @@
 			(const_int 1))
 		(lshiftrt:SI (match_dup 1)
 			     (const_int 1))))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
   [(set_attr "length" "6")])
 
@@ -3762,7 +3311,7 @@
 			   (const_int 16))
 		(ashift:SI (match_operand:SI 2 "register_operand" "r")
 			   (const_int 24))))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "#"
   "&& reload_completed"
   [(set (match_dup 3)
@@ -3785,7 +3334,7 @@
 			(const_int 16711680))
 		(ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
 			   (const_int 24))))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "#"
   "&& reload_completed"
   [(set (match_dup 3)
@@ -3808,7 +3357,7 @@
 			  (const_int 8388608))
 		 (match_operand:SI 2 "register_operand" "0")))
    (clobber (match_scratch:SI 3 "=&r"))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "#")
 
 (define_split
@@ -3817,10 +3366,9 @@
 			  (const_int 8388608))
 		 (match_dup 0)))
    (clobber (match_operand:SI 2 "register_operand" ""))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && epilogue_completed
-    && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
-    && REGNO (operands[0]) != REGNO (operands[1])"
+  "epilogue_completed
+   && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
+   && REGNO (operands[0]) != REGNO (operands[1])"
   [(parallel [(set (match_dup 3)
 		   (ashift:HI (match_dup 3)
 			      (const_int 7)))
@@ -3839,10 +3387,9 @@
 			  (const_int 8388608))
 		 (match_dup 0)))
    (clobber (match_operand:SI 2 "register_operand" ""))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && epilogue_completed
-    && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
-	 && REGNO (operands[0]) != REGNO (operands[1]))"
+  "epilogue_completed
+   && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
+	&& REGNO (operands[0]) != REGNO (operands[1]))"
   [(set (match_dup 2)
 	(match_dup 1))
    (parallel [(set (match_dup 3)
@@ -3863,7 +3410,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
 		   (const_int 7)))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 2)
@@ -3907,7 +3454,7 @@
 	(subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
 				(const_int 16)) 3))
    (clobber (match_scratch:SI 2 "=&r"))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
   [(set_attr "cc" "set_znv")
    (set_attr "length" "10")])
@@ -3917,7 +3464,7 @@
 	(subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
 				(const_int 24)) 3))
    (clobber (match_scratch:SI 2 "=&r"))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
   [(set_attr "cc" "set_znv")
    (set_attr "length" "10")])
@@ -4269,11 +3816,10 @@
    (set (match_dup 0)
 	(plus:SI (match_dup 0)
 		 (match_operand:SI 2 "register_operand" "")))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && REG_P (operands[0]) && REG_P (operands[2])
-    && REGNO (operands[0]) != REGNO (operands[2])
-    && (satisfies_constraint_L (operands[1])
-	|| satisfies_constraint_N (operands[1]))"
+  "REG_P (operands[0]) && REG_P (operands[2])
+   && REGNO (operands[0]) != REGNO (operands[2])
+   && (satisfies_constraint_L (operands[1])
+       || satisfies_constraint_N (operands[1]))"
   [(set (match_dup 0)
 	(match_dup 2))
    (set (match_dup 0)
@@ -4298,16 +3844,15 @@
    (set (match_dup 0)
 	(plus:SI (match_dup 0)
 		 (match_operand:SI 2 "const_int_operand" "")))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && operands[0] != stack_pointer_rtx
-    && REG_P (operands[0]) && REG_P (operands[1])
-    && REGNO (operands[0]) != REGNO (operands[1])
-    && !satisfies_constraint_L (operands[2])
-    && !satisfies_constraint_N (operands[2])
-    && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
-	|| (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
-	|| INTVAL (operands[2]) == 0xffff
-	|| INTVAL (operands[2]) == 0xfffe)"
+  "operands[0] != stack_pointer_rtx
+   && REG_P (operands[0]) && REG_P (operands[1])
+   && REGNO (operands[0]) != REGNO (operands[1])
+   && !satisfies_constraint_L (operands[2])
+   && !satisfies_constraint_N (operands[2])
+   && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
+       || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
+       || INTVAL (operands[2]) == 0xffff
+       || INTVAL (operands[2]) == 0xfffe)"
   [(set (match_dup 0)
 	(match_dup 2))
    (set (match_dup 0)
@@ -4337,7 +3882,7 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   [(set (match_operand:HI 0 "register_operand" "")
 	(unspec:HI [(match_dup 0)
 		    (match_dup 1)]
@@ -4363,7 +3908,7 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   [(set (match_operand:SI 0 "register_operand" "")
 	(unspec:SI [(match_dup 0)
 		    (match_dup 1)]
@@ -4388,7 +3933,7 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   [(set (cc0) (compare (match_dup 0)
 		       (const_int 0)))
    (set (pc)
@@ -4418,9 +3963,8 @@
    (set (match_operand:SI 2 "register_operand" "")
 	(and:SI (match_dup 2)
 		(const_int 255)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && !reg_overlap_mentioned_p (operands[2], operands[1])
-    && REGNO (operands[0]) == REGNO (operands[2])"
+  "!reg_overlap_mentioned_p (operands[2], operands[1])
+   && REGNO (operands[0]) == REGNO (operands[2])"
   [(set (match_dup 2)
 	(const_int 0))
    (set (strict_low_part (match_dup 0))
@@ -4433,10 +3977,9 @@
    (set (match_dup 0)
 	(and:SI (match_dup 0)
 		(const_int 255)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && !reg_overlap_mentioned_p (operands[0], operands[1])
-    && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1]))
-    && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
+  "!reg_overlap_mentioned_p (operands[0], operands[1])
+   && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1]))
+   && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
   [(set (match_dup 0)
 	(const_int 0))
    (set (strict_low_part (match_dup 2))
@@ -4452,19 +3995,18 @@
    (set (match_operand:SI 2 "register_operand" "")
 	(and:SI (match_dup 2)
 		(match_operand:SI 3 "const_int_qi_operand" "")))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && (GET_MODE (operands[0]) == QImode
-	|| GET_MODE (operands[0]) == HImode
-	|| GET_MODE (operands[0]) == SImode)
-    && GET_MODE (operands[0]) == GET_MODE (operands[1])
-    && REGNO (operands[0]) == REGNO (operands[2])
-    && !reg_overlap_mentioned_p (operands[2], operands[1])
-    && !(GET_MODE (operands[1]) != QImode
-	 && GET_CODE (operands[1]) == MEM
-	 && !offsettable_memref_p (operands[1]))
-    && !(GET_MODE (operands[1]) != QImode
-	 && GET_CODE (operands[1]) == MEM
-	 && MEM_VOLATILE_P (operands[1]))"
+  "(GET_MODE (operands[0]) == QImode
+    || GET_MODE (operands[0]) == HImode
+    || GET_MODE (operands[0]) == SImode)
+   && GET_MODE (operands[0]) == GET_MODE (operands[1])
+   && REGNO (operands[0]) == REGNO (operands[2])
+   && !reg_overlap_mentioned_p (operands[2], operands[1])
+   && !(GET_MODE (operands[1]) != QImode
+	&& GET_CODE (operands[1]) == MEM
+	&& !offsettable_memref_p (operands[1]))
+   && !(GET_MODE (operands[1]) != QImode
+	&& GET_CODE (operands[1]) == MEM
+	&& MEM_VOLATILE_P (operands[1]))"
   [(set (match_dup 2)
 	(const_int 0))
    (set (strict_low_part (match_dup 4))
@@ -4484,8 +4026,7 @@
    (set (match_dup 0)
 	(and:SI (match_dup 0)
 		(const_int 65280)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-   && !reg_overlap_mentioned_p (operands[0], operands[1])"
+  "!reg_overlap_mentioned_p (operands[0], operands[1])"
   [(set (match_dup 0)
 	(const_int 0))
    (set (zero_extract:SI (match_dup 0)
@@ -4504,11 +4045,10 @@
    (set (match_dup 0)
 	(and:SI (match_dup 0)
 		(match_operand:SI 2 "const_int_operand" "")))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && !MEM_VOLATILE_P (operands[1])
-    && offsettable_memref_p (operands[1])
-    && (INTVAL (operands[2]) & ~0xffff) == 0
-    && INTVAL (operands[2]) != 255"
+  "!MEM_VOLATILE_P (operands[1])
+   && offsettable_memref_p (operands[1])
+   && (INTVAL (operands[2]) & ~0xffff) == 0
+   && INTVAL (operands[2]) != 255"
   [(set (match_dup 3)
 	(match_dup 4))
    (set (match_dup 0)
@@ -4538,7 +4078,7 @@
    (set (cc0)
 	(compare (match_operand:HI 0 "memory_operand" "")
 		 (const_int 0)))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   [(set (match_dup 1)
 	(match_dup 0))
    (set (cc0) (compare (match_dup 1)
@@ -4550,7 +4090,7 @@
    (set (cc0)
 	(compare (match_operand:SI 0 "memory_operand" "")
 		 (const_int 0)))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   [(set (match_dup 1)
 	(match_dup 0))
    (set (cc0) (compare (match_dup 1)
@@ -4598,9 +4138,7 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && INTVAL (operands[1]) != 0
-    && peep2_reg_dead_p (1, operands[0])"
+  "INTVAL (operands[1]) != 0 && peep2_reg_dead_p (1, operands[0])"
   [(set (match_dup 0)
 	(unspec:HI [(match_dup 0)
 		    (match_dup 4)]
@@ -4634,10 +4172,9 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 3 "" ""))
 		      (pc)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && peep2_reg_dead_p (1, operands[0])
-    && (INTVAL (operands[1]) == 1
-	|| (TARGET_H8300S && INTVAL (operands[1]) == 3))"
+  "peep2_reg_dead_p (1, operands[0])
+   && (INTVAL (operands[1]) == 1
+       || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
   [(parallel [(set (match_dup 0)
 		   (ashiftrt:HI (match_dup 0)
 				(match_dup 4)))
@@ -4671,10 +4208,9 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 3 "" ""))
 		      (pc)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && peep2_reg_dead_p (1, operands[0])
-    && (INTVAL (operands[1]) == 1
-	|| (TARGET_H8300S && INTVAL (operands[1]) == 3))"
+  "peep2_reg_dead_p (1, operands[0])
+   && (INTVAL (operands[1]) == 1
+       || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
   [(parallel [(set (match_dup 0)
 		   (ashiftrt:HI (match_dup 0)
 				(match_dup 4)))
@@ -4710,7 +4246,7 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   [(set (cc0) (compare (and:HI (match_dup 0)
 			       (const_int -256))
 		       (const_int 0)))
@@ -4739,7 +4275,7 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   [(set (cc0) (compare (and:HI (match_dup 0)
 			       (const_int -256))
 		       (const_int 0)))
@@ -4833,9 +4369,7 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && INTVAL (operands[1]) != 0
-    && peep2_reg_dead_p (1, operands[0])"
+  "INTVAL (operands[1]) != 0 && peep2_reg_dead_p (1, operands[0])"
   [(set (match_dup 0)
 	(unspec:SI [(match_dup 0)
 		    (match_dup 4)]
@@ -4869,12 +4403,11 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && peep2_reg_dead_p (1, operands[0])
-    && (INTVAL (operands[1]) == -131072
-	|| INTVAL (operands[1]) == -65536
-	|| INTVAL (operands[1]) == 65536
-	|| INTVAL (operands[1]) == 131072)"
+  "peep2_reg_dead_p (1, operands[0])
+   && (INTVAL (operands[1]) == -131072
+       || INTVAL (operands[1]) == -65536
+       || INTVAL (operands[1]) == 65536
+       || INTVAL (operands[1]) == 131072)"
   [(set (match_dup 0)
 	(plus:SI (match_dup 0)
 		 (match_dup 4)))
@@ -4908,14 +4441,13 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && peep2_reg_dead_p (1, operands[0])
-    && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
-	|| (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
-	|| INTVAL (operands[1]) == 0x0000ffff)
-    && INTVAL (operands[1]) != 0
-    && INTVAL (operands[1]) != 1
-    && INTVAL (operands[1]) != 2"
+  "peep2_reg_dead_p (1, operands[0])
+   && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
+       || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
+       || INTVAL (operands[1]) == 0x0000ffff)
+   && INTVAL (operands[1]) != 0
+   && INTVAL (operands[1]) != 1
+   && INTVAL (operands[1]) != 2"
   [(set (match_dup 0)
 	(xor:SI (match_dup 0)
 		(match_dup 1)))
@@ -4947,12 +4479,11 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && peep2_reg_dead_p (1, operands[0])
-    && ((INTVAL (operands[1]) | 0x00ff) == -1
-	|| (INTVAL (operands[1]) | 0xff00) == -1)
-    && INTVAL (operands[1]) != -1
-    && INTVAL (operands[1]) != -2"
+  "peep2_reg_dead_p (1, operands[0])
+   && ((INTVAL (operands[1]) | 0x00ff) == -1
+       || (INTVAL (operands[1]) | 0xff00) == -1)
+   && INTVAL (operands[1]) != -1
+   && INTVAL (operands[1]) != -2"
   [(set (match_dup 0)
 	(xor:SI (match_dup 0)
 		(match_dup 4)))
@@ -4988,10 +4519,9 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && peep2_reg_dead_p (1, operands[0])
-    && (INTVAL (operands[1]) == -2147483647 - 1
-	|| (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
+  "peep2_reg_dead_p (1, operands[0])
+   && (INTVAL (operands[1]) == -2147483647 - 1
+       || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
   [(set (match_dup 0)
 	(rotate:SI (match_dup 0)
 		   (match_dup 4)))
@@ -5033,11 +4563,10 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 3 "" ""))
 		      (pc)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && !peep2_reg_dead_p (1, operands[0])
-    && (INTVAL (operands[1]) == 1
-	|| (TARGET_H8300S && INTVAL (operands[1]) == 3))
-    && !same_cmp_preceding_p (insn)"
+  "!peep2_reg_dead_p (1, operands[0])
+   && (INTVAL (operands[1]) == 1
+       || (TARGET_H8300S && INTVAL (operands[1]) == 3))
+   && !same_cmp_preceding_p (insn)"
   [(set (match_dup 4)
 	(match_dup 0))
    (parallel [(set (match_dup 4)
@@ -5078,11 +4607,10 @@
 		         [(cc0) (const_int 0)])
 		      (label_ref (match_operand 3 "" ""))
 		      (pc)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && !peep2_reg_dead_p (1, operands[0])
-    && (INTVAL (operands[1]) == 1
-	|| (TARGET_H8300S && INTVAL (operands[1]) == 3))
-    && !same_cmp_preceding_p (insn)"
+  "!peep2_reg_dead_p (1, operands[0])
+   && (INTVAL (operands[1]) == 1
+       || (TARGET_H8300S && INTVAL (operands[1]) == 3))
+   && !same_cmp_preceding_p (insn)"
   [(set (match_dup 4)
 	(match_dup 0))
    (parallel [(set (match_dup 4)
@@ -5120,10 +4648,9 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 3 "" ""))
 		      (pc)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && peep2_reg_dead_p (1, operands[0])
-    && (INTVAL (operands[1]) == 1
-        || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
+  "peep2_reg_dead_p (1, operands[0])
+   && (INTVAL (operands[1]) == 1
+       || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
   [(parallel [(set (match_dup 0)
 		   (ashiftrt:SI (match_dup 0)
 				(match_dup 4)))
@@ -5157,10 +4684,9 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 3 "" ""))
 		      (pc)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && peep2_reg_dead_p (1, operands[0])
-    && (INTVAL (operands[1]) == 1
-	|| (TARGET_H8300S && INTVAL (operands[1]) == 3))"
+  "peep2_reg_dead_p (1, operands[0])
+   && (INTVAL (operands[1]) == 1
+       || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
   [(parallel [(set (match_dup 0)
 		   (ashiftrt:SI (match_dup 0)
 				(match_dup 4)))
@@ -5197,15 +4723,14 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 3 "" ""))
 		      (pc)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && peep2_reg_dead_p (1, operands[0])
-    && (INTVAL (operands[1]) == 3
-	 || INTVAL (operands[1]) == 7
-	 || INTVAL (operands[1]) == 15
-	 || INTVAL (operands[1]) == 31
-	 || INTVAL (operands[1]) == 63
-	 || INTVAL (operands[1]) == 127
-	 || INTVAL (operands[1]) == 255)"
+  "peep2_reg_dead_p (1, operands[0])
+   && (INTVAL (operands[1]) == 3
+       || INTVAL (operands[1]) == 7
+       || INTVAL (operands[1]) == 15
+       || INTVAL (operands[1]) == 31
+       || INTVAL (operands[1]) == 63
+       || INTVAL (operands[1]) == 127
+       || INTVAL (operands[1]) == 255)"
   [(set (match_dup 0)
 	(and:SI (match_dup 0)
 		(match_dup 4)))
@@ -5239,15 +4764,14 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 3 "" ""))
 		      (pc)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && peep2_reg_dead_p (1, operands[0])
-    && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
-	 || INTVAL (operands[1]) == 7
-	 || INTVAL (operands[1]) == 15
-	 || INTVAL (operands[1]) == 31
-	 || INTVAL (operands[1]) == 63
-	 || INTVAL (operands[1]) == 127
-	 || INTVAL (operands[1]) == 255)"
+  "peep2_reg_dead_p (1, operands[0])
+   && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
+	|| INTVAL (operands[1]) == 7
+	|| INTVAL (operands[1]) == 15
+	|| INTVAL (operands[1]) == 31
+	|| INTVAL (operands[1]) == 63
+	|| INTVAL (operands[1]) == 127
+	|| INTVAL (operands[1]) == 255)"
   [(set (match_dup 0)
 	(and:SI (match_dup 0)
 		(match_dup 4)))
@@ -5282,7 +4806,7 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   [(set (cc0) (compare (and:SI (match_dup 0)
 			       (const_int -65536))
 		       (const_int 0)))
@@ -5311,7 +4835,7 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
-  "TARGET_H8300H || TARGET_H8300S"
+  ""
   [(set (cc0) (compare (and:SI (match_dup 0)
 			       (const_int -65536))
 		       (const_int 0)))
@@ -5348,10 +4872,9 @@
 		       [(cc0) (const_int 0)])
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
-  "(TARGET_H8300H || TARGET_H8300S)
-    && INTVAL (operands[1]) != 0
-    && !peep2_reg_dead_p (1, operands[0])
-    && !same_cmp_following_p (insn)"
+  "INTVAL (operands[1]) != 0
+   && !peep2_reg_dead_p (1, operands[0])
+   && !same_cmp_following_p (insn)"
   [(set (match_dup 4)
 	(match_dup 0))
    (set (match_dup 4)
@@ -5415,8 +4938,7 @@
 		 (const_int -4)))
    (set (mem:SI (reg:SI SP_REG))
 	(match_operand:SI 0 "register_operand" ""))]
-  "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
-    && REGNO (operands[0]) != SP_REG"
+  "!TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
   [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
 	(match_dup 0))]
   "")
@@ -5432,8 +4954,7 @@
 		 (const_int -12)))
    (set (mem:SI (reg:SI SP_REG))
 	(match_operand:SI 0 "register_operand" ""))]
-  "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
-    && REGNO (operands[0]) != SP_REG"
+  "!TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
   [(set (reg:SI SP_REG)
 	(plus:SI (reg:SI SP_REG)
 		 (const_int -4)))
diff --git a/gcc/config/h8300/predicates.md b/gcc/config/h8300/predicates.md
index 5e94611..6496992 100644
--- a/gcc/config/h8300/predicates.md
+++ b/gcc/config/h8300/predicates.md
@@ -296,30 +296,17 @@
          the negative case.  */
       if (value < 0)
 	value = -value;
-      if (TARGET_H8300H || TARGET_H8300S)
-	{
-	  /* A constant addition/subtraction takes 2 states in QImode,
-	     4 states in HImode, and 6 states in SImode.  Thus, the
-	     only case we can win is when SImode is used, in which
-	     case, two adds/subs are used, taking 4 states.  */
-	  if (mode == SImode
-	      && (value == 2 + 1
-		  || value == 4 + 1
-		  || value == 4 + 2
-		  || value == 4 + 4))
-	    return 1;
-	}
-      else
-	{
-	  /* We do not profit directly by splitting addition or
-	     subtraction of 3 and 4.  However, since these are
-	     implemented as a sequence of adds or subs, they do not
-	     clobber (cc0) unlike a sequence of add.b and add.x.  */
-	  if (mode == HImode
-	      && (value == 2 + 1
-		  || value == 2 + 2))
-	    return 1;
-	}
+
+      /* A constant addition/subtraction takes 2 states in QImode,
+	 4 states in HImode, and 6 states in SImode.  Thus, the
+	 only case we can win is when SImode is used, in which
+	 case, two adds/subs are used, taking 4 states.  */
+      if (mode == SImode
+	  && (value == 2 + 1
+	      || value == 4 + 1
+	      || value == 4 + 2
+	      || value == 4 + 4))
+	return 1;
     }
 
   return 0;
diff --git a/gcc/config/h8300/t-h8300 b/gcc/config/h8300/t-h8300
index ee34d81..62d2700 100644
--- a/gcc/config/h8300/t-h8300
+++ b/gcc/config/h8300/t-h8300
@@ -16,9 +16,8 @@
 # along with GCC; see the file COPYING3.  If not see
 # <http://www.gnu.org/licenses/>.
 
-MULTILIB_OPTIONS = mh/ms/msx mn mint32
-MULTILIB_DIRNAMES = h8300h h8300s h8sx normal int32
-MULTILIB_EXCEPTIONS = mint32 mn mn/mint32
+MULTILIB_OPTIONS = ms/msx mn mint32
+MULTILIB_DIRNAMES = h8300s h8sx normal int32
 
 s-config s-conditions s-flags s-codes s-constants s-emit s-recog \
 s-opinit s-extract s-peep s-attr s-attrtab s-output: \