diff options
Diffstat (limited to 'gcc/config/h8300/h8300.md')
| -rw-r--r-- | gcc/config/h8300/h8300.md | 1051 |
1 files changed, 286 insertions, 765 deletions
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md index a86b8ea..f87b0f7 100644 --- a/gcc/config/h8300/h8300.md +++ b/gcc/config/h8300/h8300.md @@ -167,8 +167,7 @@ (define_asm_attributes [(set (attr "length") - (cond [(match_test "TARGET_H8300") (const_int 4) - (match_test "TARGET_H8300H") (const_int 10) + (cond [(match_test "TARGET_H8300H") (const_int 10) (match_test "TARGET_H8300S") (const_int 10)] (const_int 14)))]) @@ -205,7 +204,7 @@ (define_insn "*movqi_h8nosx" [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m") (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))] - "(TARGET_H8300 || TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX + "!TARGET_H8300SX && h8300_move_ok (operands[0], operands[1])" "@ sub.b %X0,%X0 @@ -234,13 +233,7 @@ "" { enum machine_mode mode = <MODE>mode; - if (TARGET_H8300 && (mode == SImode || mode == SFmode)) - { - /* The original H8/300 needs to split up 32 bit moves. */ - if (h8300_expand_movsi (operands)) - DONE; - } - else if (!TARGET_H8300SX) + if (!TARGET_H8300SX) { /* Other H8 chips, except the H8/SX family can only handle a single memory operand, which is checked by h8300_move_ok. @@ -268,7 +261,7 @@ (define_insn "*movhi_h8nosx" [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m") (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))] - "(TARGET_H8300 || TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX + "!TARGET_H8300SX && h8300_move_ok (operands[0], operands[1])" "@ sub.w %T0,%T0 @@ -308,76 +301,6 @@ (set_attr "cc" "set_zn,set_znv,set_znv")]) ;; movsi - -(define_insn "*movsi_h8300" - [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r") - (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))] - "TARGET_H8300 - && h8300_move_ok (operands[0], operands[1])" -{ - unsigned int rn = -1; - switch (which_alternative) - { - case 0: - return "sub.w %e0,%e0\;sub.w %f0,%f0"; - case 1: - if (REGNO (operands[0]) < REGNO (operands[1])) - return "mov.w %e1,%e0\;mov.w %f1,%f0"; - else - return "mov.w %f1,%f0\;mov.w %e1,%e0"; - case 2: - /* Make sure we don't trample the register we index with. */ - if (GET_CODE (operands[1]) == MEM) - { - rtx inside = XEXP (operands[1], 0); - if (REG_P (inside)) - { - rn = REGNO (inside); - } - else if (GET_CODE (inside) == PLUS) - { - rtx lhs = XEXP (inside, 0); - rtx rhs = XEXP (inside, 1); - if (REG_P (lhs)) rn = REGNO (lhs); - if (REG_P (rhs)) rn = REGNO (rhs); - } - } - if (rn == REGNO (operands[0])) - { - /* Move the second word first. */ - return "mov.w %f1,%f0\;mov.w %e1,%e0"; - } - else - { - if (GET_CODE (operands[1]) == CONST_INT) - { - /* If either half is zero, use sub.w to clear that - half. */ - if ((INTVAL (operands[1]) & 0xffff) == 0) - return "mov.w %e1,%e0\;sub.w %f0,%f0"; - if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0) - return "sub.w %e0,%e0\;mov.w %f1,%f0"; - /* If the upper half and the lower half are the same, - copy one half to the other. */ - if ((INTVAL (operands[1]) & 0xffff) - == ((INTVAL (operands[1]) >> 16) & 0xffff)) - return "mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0"; - } - return "mov.w %e1,%e0\;mov.w %f1,%f0"; - } - case 3: - return "mov.w %e1,%e0\;mov.w %f1,%f0"; - case 4: - return "mov.w %f1,%T0\;mov.w %e1,%T0"; - case 5: - return "mov.w %T1,%e0\;mov.w %T1,%f0"; - default: - gcc_unreachable (); - } -} - [(set (attr "length") - (symbol_ref "compute_mov_length (operands)"))]) - (define_insn "*movsi_h8300hs" [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r") (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))] @@ -476,65 +399,10 @@ (include "mova.md") -(define_insn "*movsf_h8300" - [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r") - (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))] - "TARGET_H8300 - && (register_operand (operands[0], SFmode) - || register_operand (operands[1], SFmode))" -{ - /* Copy of the movsi stuff. */ - unsigned int rn = -1; - switch (which_alternative) - { - case 0: - return "sub.w %e0,%e0\;sub.w %f0,%f0"; - case 1: - if (REGNO (operands[0]) < REGNO (operands[1])) - return "mov.w %e1,%e0\;mov.w %f1,%f0"; - else - return "mov.w %f1,%f0\;mov.w %e1,%e0"; - case 2: - /* Make sure we don't trample the register we index with. */ - if (GET_CODE (operands[1]) == MEM) - { - rtx inside = XEXP (operands[1], 0); - if (REG_P (inside)) - { - rn = REGNO (inside); - } - else if (GET_CODE (inside) == PLUS) - { - rtx lhs = XEXP (inside, 0); - rtx rhs = XEXP (inside, 1); - if (REG_P (lhs)) rn = REGNO (lhs); - if (REG_P (rhs)) rn = REGNO (rhs); - } - } - if (rn == REGNO (operands[0])) - /* Move the second word first. */ - return "mov.w %f1,%f0\;mov.w %e1,%e0"; - else - /* Move the first word first. */ - return "mov.w %e1,%e0\;mov.w %f1,%f0"; - - case 3: - return "mov.w %e1,%e0\;mov.w %f1,%f0"; - case 4: - return "mov.w %f1,%T0\;mov.w %e1,%T0"; - case 5: - return "mov.w %T1,%e0\;mov.w %T1,%f0"; - default: - gcc_unreachable (); - } -} - [(set (attr "length") - (symbol_ref "compute_mov_length (operands)"))]) - (define_insn "*movsf_h8300hs" [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r") (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))] - "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX + "!TARGET_H8300SX && (register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode))" "@ @@ -552,23 +420,13 @@ ;; PUSH INSTRUCTIONS ;; ---------------------------------------------------------------------- -(define_insn "*pushqi1_h8300" - [(set (mem:QI - (pre_modify:HI - (reg:HI SP_REG) - (plus:HI (reg:HI SP_REG) (const_int -2)))) - (match_operand:QI 0 "register_no_sp_elim_operand" "r"))] - "TARGET_H8300" - "mov.w\\t%T0,@-r7" - [(set_attr "length" "2")]) - (define_insn "*push1_h8300hs_<QHI:mode>" [(set (mem:QHI (pre_modify:P (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -4)))) (match_operand:QHI 0 "register_no_sp_elim_operand" "r"))] - "TARGET_H8300H || TARGET_H8300S" + "" "mov.l\\t%S0,@-er7" [(set_attr "length" "4")]) @@ -577,17 +435,6 @@ ;; TEST INSTRUCTIONS ;; ---------------------------------------------------------------------- -(define_insn "" - [(set (cc0) - (compare (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "r,U") - (const_int 1) - (match_operand 1 "const_int_operand" "n,n")) - (const_int 0)))] - "TARGET_H8300" - "btst %Z1,%Y0" - [(set_attr "length" "2,4") - (set_attr "cc" "set_zn,set_zn")]) - (define_insn_and_split "*tst_extzv_1_n" [(set (cc0) (compare (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>") @@ -595,7 +442,7 @@ (match_operand 1 "const_int_operand" "n,n,n")) (const_int 0))) (clobber (match_scratch:QI 2 "=X,X,&r"))] - "TARGET_H8300H || TARGET_H8300S" + "" "@ btst\\t%Z1,%Y0 btst\\t%Z1,%Y0 @@ -619,8 +466,7 @@ (const_int 1) (match_operand 1 "const_int_operand" "n")) (const_int 0)))] - "(TARGET_H8300 || TARGET_H8300H || TARGET_H8300S) - && INTVAL (operands[1]) <= 15" + "INTVAL (operands[1]) <= 15" "btst %Z1,%Y0" [(set_attr "length" "2") (set_attr "cc" "set_zn")]) @@ -632,8 +478,7 @@ (match_operand 1 "const_int_operand" "n")) (const_int 0))) (clobber (match_scratch:SI 2 "=&r"))] - "(TARGET_H8300H || TARGET_H8300S) - && INTVAL (operands[1]) >= 16" + "INTVAL (operands[1]) >= 16" "#" "&& reload_completed" [(set (match_dup 2) @@ -657,7 +502,7 @@ (and:SI (match_operand:SI 1 "register_operand" "r") (const_int 7))) (const_int 0)))] - "TARGET_H8300H || TARGET_H8300S" + "" "btst %w1,%w0" [(set_attr "length" "2") (set_attr "cc" "set_zn")]) @@ -670,7 +515,7 @@ (const_int 7))) (const_int 0))) (clobber (match_scratch:QI 2 "=X,X,&r"))] - "TARGET_H8300H || TARGET_H8300S" + "" "@ btst\\t%w1,%X0 btst\\t%w1,%X0 @@ -719,7 +564,7 @@ [(set (cc0) (compare (match_operand:SI 0 "register_operand" "r") (const_int 0)))] - "TARGET_H8300H || TARGET_H8300S" + "" "mov.l %S0,%S0" [(set_attr "length" "2") (set_attr "cc" "set_znv")]) @@ -743,20 +588,11 @@ [(set_attr "length_table" "add") (set_attr "cc" "compare")]) -(define_insn "*cmphi_h8300_znvc" - [(set (cc0) - (compare (match_operand:HI 0 "register_operand" "r") - (match_operand:HI 1 "register_operand" "r")))] - "TARGET_H8300" - "cmp.w %T1,%T0" - [(set_attr "length" "2") - (set_attr "cc" "compare")]) - (define_insn "*cmphi_h8300hs_znvc" [(set (cc0) (compare (match_operand:HI 0 "h8300_dst_operand" "rU,rQ") (match_operand:HI 1 "h8300_src_operand" "P3>X,rQi")))] - "TARGET_H8300H || TARGET_H8300S" + "" { switch (which_alternative) { @@ -778,7 +614,7 @@ [(set (cc0) (compare (match_operand:SI 0 "h8300_dst_operand" "r,rQ") (match_operand:SI 1 "h8300_src_operand" "P3>X,rQi")))] - "TARGET_H8300H || TARGET_H8300S" + "" { switch (which_alternative) { @@ -817,57 +653,11 @@ [(set_attr "length_table" "add") (set_attr "cc" "set_zn")]) -(define_insn "*addhi3_h8300" - [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r") - (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0") - (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))] - "TARGET_H8300" - "@ - adds %2,%T0 - subs %G2,%T0 - add.b %t2,%t0 - add.b %s2,%s0\;addx %t2,%t0 - add.w %T2,%T0" - [(set_attr "length" "2,2,2,4,2") - (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")]) - -;; This splitter is very important to make the stack adjustment -;; interrupt-safe. The combination of add.b and addx is unsafe! -;; -;; We apply this split after the peephole2 pass so that we won't end -;; up creating too many adds/subs when a scratch register is -;; available, which is actually a common case because stack unrolling -;; tends to happen immediately after a function call. - -(define_split - [(set (match_operand:HI 0 "stack_pointer_operand" "") - (plus:HI (match_dup 0) - (match_operand 1 "const_int_gt_2_operand" "")))] - "TARGET_H8300 && epilogue_completed" - [(const_int 0)] - { - split_adds_subs (HImode, operands); - DONE; - }) - -(define_peephole2 - [(match_scratch:HI 2 "r") - (set (match_operand:HI 0 "stack_pointer_operand" "") - (plus:HI (match_dup 0) - (match_operand:HI 1 "const_int_ge_8_operand" "")))] - "TARGET_H8300" - [(set (match_dup 2) - (match_dup 1)) - (set (match_dup 0) - (plus:HI (match_dup 0) - (match_dup 2)))] - "") - (define_insn "*addhi3_h8300hs" [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r") (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0") (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))] - "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX" + "!TARGET_H8300SX" "@ adds %2,%S0 subs %G2,%S0 @@ -882,7 +672,7 @@ (unspec:HSI [(match_operand:HSI 1 "register_operand" "0,0") (match_operand:HSI 2 "incdec_operand" "M,O")] UNSPEC_INCDEC))] - "TARGET_H8300H || TARGET_H8300S" + "" { if (which_alternative == 0) return <MODE>mode == HImode ? "inc.w\t%2,%T0" : "inc.l\t%2,%S0"; @@ -919,24 +709,11 @@ }) -(define_insn "*addsi_h8300" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (plus:SI (match_operand:SI 1 "register_operand" "%0,0") - (match_operand:SI 2 "h8300_src_operand" "n,r")))] - "TARGET_H8300" -{ - return output_plussi (operands); -} - [(set (attr "length") - (symbol_ref "compute_plussi_length (operands)")) - (set (attr "cc") - (symbol_ref "compute_plussi_cc (operands)"))]) - (define_insn "*addsi_h8300hs" [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ") (plus:SI (match_operand:SI 1 "h8300_dst_operand" "%0,0") (match_operand:SI 2 "h8300_src_operand" "i,rQ")))] - "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)" + "h8300_operands_match_p (operands)" { return output_plussi (operands); } @@ -949,7 +726,7 @@ [(set (match_operand:SI 0 "register_operand" "") (plus:SI (match_dup 0) (match_operand:SI 1 "two_insn_adds_subs_operand" "")))] - "TARGET_H8300H || TARGET_H8300S" + "" [(const_int 0)] { split_adds_subs (SImode, operands); @@ -966,8 +743,6 @@ (match_operand:QHSI 2 "h8300_src_operand" "")))] "" { - if (TARGET_H8300 && <MODE>mode == SImode) - operands[2] = force_reg (SImode, operands[2]); }) (define_insn "*subqi3" @@ -979,22 +754,11 @@ [(set_attr "length_table" "add") (set_attr "cc" "set_zn")]) -(define_insn "*subhi3_h8300" - [(set (match_operand:HI 0 "register_operand" "=r,r") - (minus:HI (match_operand:HI 1 "register_operand" "0,0") - (match_operand:HI 2 "h8300_src_operand" "r,n")))] - "TARGET_H8300" - "@ - sub.w %T2,%T0 - add.b %E2,%s0\;addx %F2,%t0" - [(set_attr "length" "2,4") - (set_attr "cc" "set_zn,clobber")]) - (define_insn "*sub<mode>3_h8300hs" [(set (match_operand:HSI 0 "h8300_dst_operand" "=rQ,rQ") (minus:HSI (match_operand:HSI 1 "h8300_dst_operand" "0,0") (match_operand:HSI 2 "h8300_src_operand" "rQ,i")))] - "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)" + "h8300_operands_match_p (operands)" { if (<MODE>mode == HImode) return "sub.w %T2,%T0"; @@ -1005,14 +769,6 @@ [(set_attr "length_table" "add") (set_attr "cc" "set_zn")]) -(define_insn "*subsi3_h8300" - [(set (match_operand:SI 0 "register_operand" "=r") - (minus:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "register_operand" "r")))] - "TARGET_H8300" - "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0" - [(set_attr "length" "6")]) - ;; ---------------------------------------------------------------------- ;; MULTIPLY INSTRUCTIONS @@ -1025,7 +781,7 @@ (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "")) ;; intentionally-mismatched modes (match_operand:QI 2 "reg_or_nibble_operand" "")))] - "TARGET_H8300H || TARGET_H8300S" + "" { if (GET_MODE (operands[2]) != VOIDmode) operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]); @@ -1044,7 +800,7 @@ [(set (match_operand:HI 0 "register_operand" "=r") (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0")) (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))] - "TARGET_H8300H || TARGET_H8300S" + "" "mulxs.b %X2,%T0" [(set_attr "length" "4") (set_attr "cc" "set_zn")]) @@ -1054,7 +810,7 @@ (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "")) ;; intentionally-mismatched modes (match_operand:HI 2 "reg_or_nibble_operand" "")))] - "TARGET_H8300H || TARGET_H8300S" + "" { if (GET_MODE (operands[2]) != VOIDmode) operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]); @@ -1073,7 +829,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0")) (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))] - "TARGET_H8300H || TARGET_H8300S" + "" "mulxs.w %T2,%S0" [(set_attr "length" "4") (set_attr "cc" "set_zn")]) @@ -1083,7 +839,7 @@ (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "")) ;; intentionally-mismatched modes (match_operand:QI 2 "reg_or_nibble_operand" "")))] - "TARGET_H8300H || TARGET_H8300S" + "" { if (GET_MODE (operands[2]) != VOIDmode) operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]); @@ -1112,7 +868,7 @@ (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "")) ;; intentionally-mismatched modes (match_operand:HI 2 "reg_or_nibble_operand" "")))] - "TARGET_H8300H || TARGET_H8300S" + "" { if (GET_MODE (operands[2]) != VOIDmode) operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]); @@ -1131,7 +887,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0")) (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))] - "TARGET_H8300H || TARGET_H8300S" + "" "mulxu.w %T2,%S0" [(set_attr "length" "2") (set_attr "cc" "none_0hit")]) @@ -1259,7 +1015,7 @@ (mod:HI (match_dup 1) (sign_extend:HI (match_dup 2)))))] - "TARGET_H8300H || TARGET_H8300S" + "" { if (find_reg_note (insn, REG_UNUSED, operands[3])) return "divxs.b\\t%X2,%T0"; @@ -1279,7 +1035,7 @@ (umod:SI (match_dup 1) (zero_extend:SI (match_dup 2)))))] - "TARGET_H8300H || TARGET_H8300S" + "" { if (find_reg_note (insn, REG_UNUSED, operands[3])) return "divxu.w\\t%T2,%S0"; @@ -1299,7 +1055,7 @@ (mod:SI (match_dup 1) (sign_extend:SI (match_dup 2)))))] - "TARGET_H8300H || TARGET_H8300S" + "" { if (find_reg_note (insn, REG_UNUSED, operands[3])) return "divxs.w\\t%T2,%S0"; @@ -1460,7 +1216,7 @@ || single_one_operand (operands[2], QImode)" { if (which_alternative == 0) - return <CODE> == IOR ? "bset\\t%V2,%R0" : "bnot\\t%V2,%R0"; + return <CODE> == IOR ? "bset\\t%V2,%R0" : "bnot\\t%V2,%R0"; else if (which_alternative == 1) return <CODE> == IOR ? "or\\t%X2,%X0" : "xor\\t%X2,%X0"; gcc_unreachable (); @@ -1500,24 +1256,7 @@ [(set (match_operand:QHSIF 0 "register_operand" "") (neg:QHSIF (match_operand:QHSIF 1 "register_operand" "")))] "" - { - enum machine_mode mode = <MODE>mode; - if (TARGET_H8300) - { - if (mode == QImode || mode == SFmode) - ; - else if (mode == HImode) - { - emit_insn (gen_neghi2_h8300 (operands[0], operands[1])); - DONE; - } - else if (mode == SImode) - { - emit_insn (gen_negsi2_h8300 (operands[0], operands[1])); - DONE; - } - } - }) + { }) (define_insn "*negqi2" [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ") @@ -1541,7 +1280,7 @@ (define_insn "*neghi2_h8300hs" [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ") (neg:HI (match_operand:HI 1 "h8300_dst_operand" "0")))] - "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)" + "h8300_operands_match_p (operands)" "neg.w %T0" [(set_attr "length_table" "unary") (set_attr "cc" "set_zn")]) @@ -1549,24 +1288,18 @@ (define_insn "*negsi2_h8300hs" [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ") (neg:SI (match_operand:SI 1 "h8300_dst_operand" "0")))] - "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)" + "h8300_operands_match_p (operands)" "neg.l %S0" [(set_attr "length_table" "unary") (set_attr "cc" "set_zn")]) -(define_insn "*negsf2_h8300" - [(set (match_operand:SF 0 "register_operand" "=r") - (neg:SF (match_operand:SF 1 "register_operand" "0")))] - "TARGET_H8300" - "xor.b\\t#128,%z0" - [(set_attr "length" "2")]) - (define_insn "*negsf2_h8300hs" [(set (match_operand:SF 0 "register_operand" "=r") - (neg:SF (match_operand:SF 1 "register_operand" "0")))] + (neg:SF (match_operand:SF 1 "register_operand" "0")))] "TARGET_H8300H || TARGET_H8300S" "xor.w\\t#32768,%e0" [(set_attr "length" "4")]) + ;; ---------------------------------------------------------------------- ;; ABSOLUTE VALUE INSTRUCTIONS @@ -1578,17 +1311,10 @@ "" "") -(define_insn "*abssf2_h8300" - [(set (match_operand:SF 0 "register_operand" "=r") - (abs:SF (match_operand:SF 1 "register_operand" "0")))] - "TARGET_H8300" - "and.b\\t#127,%z0" - [(set_attr "length" "2")]) - (define_insn "*abssf2_h8300hs" [(set (match_operand:SF 0 "register_operand" "=r") (abs:SF (match_operand:SF 1 "register_operand" "0")))] - "TARGET_H8300H || TARGET_H8300S" + "" "and.w\\t#32767,%e0" [(set_attr "length" "4")]) @@ -1610,32 +1336,18 @@ [(set_attr "length_table" "unary") (set_attr "cc" "set_znv")]) -(define_insn "*one_cmplhi2_h8300" - [(set (match_operand:HI 0 "register_operand" "=r") - (not:HI (match_operand:HI 1 "register_operand" "0")))] - "TARGET_H8300" - "not %s0\;not %t0" - [(set_attr "length" "4")]) - (define_insn "*one_cmplhi2_h8300hs" [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ") (not:HI (match_operand:HI 1 "h8300_dst_operand" "0")))] - "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)" + "h8300_operands_match_p (operands)" "not.w %T0" [(set_attr "cc" "set_znv") (set_attr "length_table" "unary")]) -(define_insn "*one_cmplsi2_h8300" - [(set (match_operand:SI 0 "register_operand" "=r") - (not:SI (match_operand:SI 1 "register_operand" "0")))] - "TARGET_H8300" - "not %w0\;not %x0\;not %y0\;not %z0" - [(set_attr "length" "8")]) - (define_insn "*one_cmplsi2_h8300hs" [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ") (not:SI (match_operand:SI 1 "h8300_dst_operand" "0")))] - "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)" + "h8300_operands_match_p (operands)" "not.l %S0" [(set_attr "cc" "set_znv") (set_attr "length_table" "unary")]) @@ -1664,11 +1376,6 @@ (use (match_operand 3 ""))] "" { - /* Force operand1 into a register if we're compiling - for the H8/300. */ - if ((GET_CODE (operands[2]) != REG && operands[2] != const0_rtx) - && TARGET_H8300) - operands[2] = force_reg (HImode, operands[2]); h8300_expand_branch (operands); DONE; }) @@ -1678,7 +1385,7 @@ [(match_operand:SI 1 "h8300_dst_operand" "") (match_operand:SI 2 "h8300_src_operand" "")])) (use (match_operand 3 ""))] - "TARGET_H8300H || TARGET_H8300S" + "" { h8300_expand_branch (operands); DONE; @@ -1843,18 +1550,10 @@ "" "") -(define_insn "*tablejump_h8300" - [(set (pc) (match_operand:HI 0 "register_operand" "r")) - (use (label_ref (match_operand 1 "" "")))] - "TARGET_H8300" - "jmp @%0" - [(set_attr "cc" "none") - (set_attr "length" "2")]) - (define_insn "*tablejump_h8300hs_advanced" [(set (pc) (match_operand:SI 0 "register_operand" "r")) (use (label_ref (match_operand 1 "" "")))] - "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE" + "!TARGET_NORMAL_MODE" "jmp @%0" [(set_attr "cc" "none") (set_attr "length" "2")]) @@ -1862,7 +1561,7 @@ (define_insn "*tablejump_h8300hs_normal" [(set (pc) (match_operand:HI 0 "register_operand" "r")) (use (label_ref (match_operand 1 "" "")))] - "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE" + "TARGET_NORMAL_MODE" "jmp @%S0" [(set_attr "cc" "none") (set_attr "length" "2")]) @@ -1874,23 +1573,16 @@ "" "") -(define_insn "*indirect_jump_h8300" - [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))] - "TARGET_H8300" - "jmp @%0" - [(set_attr "cc" "none") - (set_attr "length" "2")]) - (define_insn "*indirect_jump_h8300hs_advanced" [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))] - "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE" + "!TARGET_NORMAL_MODE" "jmp @%0" [(set_attr "cc" "none") (set_attr "length" "2")]) (define_insn "*indirect_jump_h8300hs_normal" [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))] - "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE" + "TARGET_NORMAL_MODE" "jmp @%S0" [(set_attr "cc" "none") (set_attr "length" "2")]) @@ -1980,12 +1672,6 @@ ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS ;; ---------------------------------------------------------------------- -(define_expand "push_h8300" - [(set (mem:HI (pre_dec:HI (reg:HI SP_REG))) - (match_operand:HI 0 "register_operand" ""))] - "TARGET_H8300" - "") - (define_expand "push_h8300hs_advanced" [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_operand:SI 0 "register_operand" ""))] @@ -1998,12 +1684,6 @@ "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE" "") -(define_expand "pop_h8300" - [(set (match_operand:HI 0 "register_operand" "") - (mem:HI (post_inc:HI (reg:HI SP_REG))))] - "TARGET_H8300" - "") - (define_expand "pop_h8300hs_advanced" [(set (match_operand:SI 0 "register_operand" "") (mem:SI (post_inc:SI (reg:SI SP_REG))))] @@ -2100,9 +1780,7 @@ [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)] "" { - if (TARGET_H8300) - return "subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr"; - else if (TARGET_H8300H && TARGET_NORMAL_MODE) + if (TARGET_H8300H && TARGET_NORMAL_MODE) return "subs\\t#2,er7\;mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr"; else if (TARGET_H8300H) return "mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr"; @@ -2131,19 +1809,10 @@ operands[1] = force_reg (QImode, operands[1]); }) -(define_insn "*zero_extendqihi2_h8300" - [(set (match_operand:HI 0 "register_operand" "=r,r") - (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))] - "TARGET_H8300" - "@ - mov.b #0,%t0 - #" - [(set_attr "length" "2,10")]) - (define_insn "*zero_extendqihi2_h8300hs" [(set (match_operand:HI 0 "register_operand" "=r,r") (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))] - "TARGET_H8300H || TARGET_H8300S" + "" "@ extu.w %T0 #" @@ -2167,26 +1836,16 @@ operands[2] = gen_rtx_REG (QImode, REGNO (operands[0])); }) - -(define_insn "*zero_extendqisi2_h8300" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))] - "TARGET_H8300" - "@ - mov.b #0,%x0\;sub.w %e0,%e0 - mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0" - [(set_attr "length" "4,8")]) - (define_insn "*zero_extendqisi2_h8300hs" [(set (match_operand:SI 0 "register_operand" "=r,r") (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))] - "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX" + "!TARGET_H8300SX" "#") (define_split [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))] - "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX + "!TARGET_H8300SX && reg_overlap_mentioned_p (operands[0], operands[1]) && reload_completed" [(set (match_dup 2) @@ -2203,7 +1862,7 @@ (define_split [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))] - "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX + "!TARGET_H8300SX && !reg_overlap_mentioned_p (operands[0], operands[1]) && reload_completed" [(set (match_dup 0) @@ -2228,21 +1887,10 @@ "" "") -;; %e prints the high part of a CONST_INT, not the low part. Arggh. -(define_insn "*zero_extendhisi2_h8300" - [(set (match_operand:SI 0 "register_operand" "=r,r,r") - (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))] - "TARGET_H8300" - "@ - sub.w %e0,%e0 - mov.w %f1,%f0\;sub.w %e0,%e0 - mov.w %e1,%f0\;sub.w %e0,%e0" - [(set_attr "length" "2,4,6")]) - (define_insn "*zero_extendhisi2_h8300hs" [(set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))] - "TARGET_H8300H || TARGET_H8300S" + "" "extu.l %S0" [(set_attr "length" "2") (set_attr "cc" "set_znv")]) @@ -2253,32 +1901,14 @@ "" "") -(define_insn "*extendqihi2_h8300" - [(set (match_operand:HI 0 "register_operand" "=r,r") - (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))] - "TARGET_H8300" - "@ - bld #7,%s0\;subx %t0,%t0 - mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0" - [(set_attr "length" "4,8")]) - (define_insn "*extendqihi2_h8300hs" [(set (match_operand:HI 0 "register_operand" "=r") (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))] - "TARGET_H8300H || TARGET_H8300S" + "" "exts.w %T0" [(set_attr "length" "2") (set_attr "cc" "set_znv")]) -(define_insn "*extendqisi2_h8300" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))] - "TARGET_H8300" - "@ - bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0 - mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0" - [(set_attr "length" "8,12")]) - ;; The following pattern is needed because without the pattern, the ;; combiner would split (sign_extend:SI (reg:QI)) into two 24-bit ;; shifts, one ashift and one ashiftrt. @@ -2286,7 +1916,7 @@ (define_insn_and_split "*extendqisi2_h8300hs" [(set (match_operand:SI 0 "register_operand" "=r") (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))] - "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX" + "!TARGET_H8300SX" "#" "&& reload_completed" [(set (match_dup 2) @@ -2311,19 +1941,10 @@ "" "") -(define_insn "*extendhisi2_h8300" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))] - "TARGET_H8300" - "@ - bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0 - mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0" - [(set_attr "length" "6,10")]) - (define_insn "*extendhisi2_h8300hs" [(set (match_operand:SI 0 "register_operand" "=r") (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))] - "TARGET_H8300H || TARGET_H8300S" + "" "exts.l %S0" [(set_attr "length" "2") (set_attr "cc" "set_znv")]) @@ -2654,7 +2275,7 @@ [(set (match_operand:SI 0 "register_operand" "") (rotate:SI (match_operand:SI 1 "register_operand" "") (match_operand:QI 2 "nonmemory_operand" "")))] - "TARGET_H8300H || TARGET_H8300S" + "" { if (expand_a_rotate (operands)) DONE; @@ -2664,7 +2285,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (rotate:SI (match_operand:SI 1 "register_operand" "0") (match_operand:QI 2 "immediate_operand" "")))] - "TARGET_H8300H || TARGET_H8300S" + "" { return output_a_rotate (ROTATE, operands); } @@ -2685,19 +2306,6 @@ ;; canonicalize the form better. ;; -;; Normal loads with a 16bit destination. -;; - -(define_insn "" - [(set (match_operand:HI 0 "register_operand" "=&r") - (zero_extract:HI (match_operand:HI 1 "register_operand" "r") - (const_int 1) - (match_operand:HI 2 "immediate_operand" "n")))] - "TARGET_H8300" - "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0" - [(set_attr "length" "6")]) - -;; ;; Inverted loads with a 16bit destination. ;; @@ -2707,7 +2315,7 @@ (match_operand:HI 3 "const_int_operand" "n")) (const_int 1) (match_operand:HI 2 "const_int_operand" "n")))] - "(TARGET_H8300 || TARGET_H8300SX) + "(TARGET_H8300SX) && (1 << INTVAL (operands[2])) == INTVAL (operands[3])" "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0" [(set_attr "length" "8")]) @@ -2716,23 +2324,12 @@ ;; Normal loads with a 32bit destination. ;; -(define_insn "*extzv_1_r_h8300" - [(set (match_operand:SI 0 "register_operand" "=&r") - (zero_extract:SI (match_operand:HI 1 "register_operand" "r") - (const_int 1) - (match_operand 2 "const_int_operand" "n")))] - "TARGET_H8300 && INTVAL (operands[2]) < 16" -{ - return output_simode_bld (0, operands); -} - [(set_attr "length" "8")]) - (define_insn "*extzv_1_r_h8300hs" [(set (match_operand:SI 0 "register_operand" "=r,r") (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r") (const_int 1) (match_operand 2 "const_int_operand" "n,n")))] - "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16" + "INTVAL (operands[2]) < 16" { return output_simode_bld (0, operands); } @@ -2743,26 +2340,13 @@ ;; Inverted loads with a 32bit destination. ;; -(define_insn "*extzv_1_r_inv_h8300" - [(set (match_operand:SI 0 "register_operand" "=&r") - (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r") - (match_operand:HI 3 "const_int_operand" "n")) - (const_int 1) - (match_operand 2 "const_int_operand" "n")))] - "TARGET_H8300 && INTVAL (operands[2]) < 16 - && (1 << INTVAL (operands[2])) == INTVAL (operands[3])" -{ - return output_simode_bld (1, operands); -} - [(set_attr "length" "8")]) - (define_insn "*extzv_1_r_inv_h8300hs" [(set (match_operand:SI 0 "register_operand" "=r,r") (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r") (match_operand 3 "const_int_operand" "n,n")) (const_int 1) (match_operand 2 "const_int_operand" "n,n")))] - "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16 + "INTVAL (operands[2]) < 16 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])" { return output_simode_bld (1, operands); @@ -2775,61 +2359,46 @@ (match_operand:HI 1 "general_operand" "") (match_operand:HI 2 "general_operand" "")) (match_operand:HI 3 "general_operand" ""))] - "TARGET_H8300 || TARGET_H8300SX" + "TARGET_H8300SX" { - if (TARGET_H8300SX) + if (GET_CODE (operands[1]) == CONST_INT + && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[1]) <= 8 + && INTVAL (operands[2]) >= 0 + && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8 + && memory_operand (operands[0], GET_MODE (operands[0]))) { - if (GET_CODE (operands[1]) == CONST_INT - && GET_CODE (operands[2]) == CONST_INT - && INTVAL (operands[1]) <= 8 - && INTVAL (operands[2]) >= 0 - && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8 - && memory_operand (operands[0], GET_MODE (operands[0]))) + /* If the source operand is zero, it's better to use AND rather + than BFST. Likewise OR if the operand is all ones. */ + if (GET_CODE (operands[3]) == CONST_INT) + { + HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1; + if ((INTVAL (operands[3]) & mask) == 0) + FAIL; + if ((INTVAL (operands[3]) & mask) == mask) + FAIL; + } + if (! bit_memory_operand (operands[0], GET_MODE (operands[0]))) + { + if (!can_create_pseudo_p ()) + FAIL; + operands[0] = replace_equiv_address (operands[0], force_reg (Pmode, + XEXP (operands[0], 0))); + } + operands[3] = gen_lowpart (QImode, operands[3]); + if (! operands[3]) + FAIL; + if (! register_operand (operands[3], QImode)) { - /* If the source operand is zero, it's better to use AND rather - than BFST. Likewise OR if the operand is all ones. */ - if (GET_CODE (operands[3]) == CONST_INT) - { - HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1; - if ((INTVAL (operands[3]) & mask) == 0) - FAIL; - if ((INTVAL (operands[3]) & mask) == mask) - FAIL; - } - if (! bit_memory_operand (operands[0], GET_MODE (operands[0]))) - { - if (!can_create_pseudo_p ()) - FAIL; - operands[0] = replace_equiv_address (operands[0], force_reg (Pmode, - XEXP (operands[0], 0))); - } - operands[3] = gen_lowpart (QImode, operands[3]); - if (! operands[3]) + if (!can_create_pseudo_p ()) FAIL; - if (! register_operand (operands[3], QImode)) - { - if (!can_create_pseudo_p ()) - FAIL; - operands[3] = force_reg (QImode, operands[3]); - } - emit_insn (gen_bfst (adjust_address (operands[0], QImode, 0), - operands[3], operands[1], operands[2])); - DONE; + operands[3] = force_reg (QImode, operands[3]); } - FAIL; + emit_insn (gen_bfst (adjust_address (operands[0], QImode, 0), + operands[3], operands[1], operands[2])); + DONE; } - - /* We only have single bit bit-field instructions. */ - if (INTVAL (operands[1]) != 1) - FAIL; - - /* For now, we don't allow memory operands. */ - if (GET_CODE (operands[0]) == MEM - || GET_CODE (operands[3]) == MEM) - FAIL; - - if (GET_CODE (operands[3]) != REG) - operands[3] = force_reg (HImode, operands[3]); + FAIL; }) (define_insn "" @@ -2846,56 +2415,45 @@ (zero_extract:HI (match_operand:HI 1 "bit_operand" "") (match_operand:HI 2 "general_operand" "") (match_operand:HI 3 "general_operand" "")))] - "TARGET_H8300 || TARGET_H8300SX" + "TARGET_H8300SX" { - if (TARGET_H8300SX) + if (GET_CODE (operands[2]) == CONST_INT + && GET_CODE (operands[3]) == CONST_INT + && INTVAL (operands[2]) <= 8 + && INTVAL (operands[3]) >= 0 + && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8 + && memory_operand (operands[1], QImode)) { - if (GET_CODE (operands[2]) == CONST_INT - && GET_CODE (operands[3]) == CONST_INT - && INTVAL (operands[2]) <= 8 - && INTVAL (operands[3]) >= 0 - && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8 - && memory_operand (operands[1], QImode)) + rtx temp; + + /* Optimize the case where we're extracting into a paradoxical + subreg. It's only necessary to extend to the inner reg. */ + if (GET_CODE (operands[0]) == SUBREG + && subreg_lowpart_p (operands[0]) + && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) + < GET_MODE_SIZE (GET_MODE (operands[0]))) + && (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0]))) + == MODE_INT)) + operands[0] = SUBREG_REG (operands[0]); + + if (!can_create_pseudo_p ()) + temp = gen_lowpart (QImode, operands[0]); + else + temp = gen_reg_rtx (QImode); + if (! temp) + FAIL; + if (! bit_memory_operand (operands[1], QImode)) { - rtx temp; - - /* Optimize the case where we're extracting into a paradoxical - subreg. It's only necessary to extend to the inner reg. */ - if (GET_CODE (operands[0]) == SUBREG - && subreg_lowpart_p (operands[0]) - && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) - < GET_MODE_SIZE (GET_MODE (operands[0]))) - && (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0]))) - == MODE_INT)) - operands[0] = SUBREG_REG (operands[0]); - if (!can_create_pseudo_p ()) - temp = gen_lowpart (QImode, operands[0]); - else - temp = gen_reg_rtx (QImode); - if (! temp) FAIL; - if (! bit_memory_operand (operands[1], QImode)) - { - if (!can_create_pseudo_p ()) - FAIL; - operands[1] = replace_equiv_address (operands[1], - force_reg (Pmode, XEXP (operands[1], 0))); - } - emit_insn (gen_bfld (temp, operands[1], operands[2], operands[3])); - convert_move (operands[0], temp, 1); - DONE; - } - FAIL; + operands[1] = replace_equiv_address (operands[1], + force_reg (Pmode, XEXP (operands[1], 0))); + } + emit_insn (gen_bfld (temp, operands[1], operands[2], operands[3])); + convert_move (operands[0], temp, 1); + DONE; } - - /* We only have single bit bit-field instructions. */ - if (INTVAL (operands[2]) != 1) - FAIL; - - /* For now, we don't allow memory operands. */ - if (GET_CODE (operands[1]) == MEM) - FAIL; + FAIL; }) ;; BAND, BOR, and BXOR patterns @@ -3186,7 +2744,7 @@ (const_int 1) (match_operand:SI 1 "const_int_operand" "n")) (match_operand:SI 2 "register_operand" "r"))] - "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[1]) < 16" + "INTVAL (operands[1]) < 16" "bld\\t#0,%w2\;bst\\t%Z1,%Y0" [(set_attr "length" "4")]) @@ -3196,9 +2754,7 @@ (match_operand:SI 1 "const_int_operand" "n")) (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") (match_operand:SI 3 "const_int_operand" "n")))] - "(TARGET_H8300H || TARGET_H8300S) - && INTVAL (operands[1]) < 16 - && INTVAL (operands[3]) < 16" + "INTVAL (operands[1]) < 16 && INTVAL (operands[3]) < 16" "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0" [(set_attr "length" "4")]) @@ -3208,7 +2764,7 @@ (match_operand:SI 1 "const_int_operand" "n")) (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") (const_int 16)))] - "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[1]) < 16" + "INTVAL (operands[1]) < 16" "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0" [(set_attr "length" "6")]) @@ -3217,7 +2773,7 @@ (const_int 8) (const_int 8)) (match_operand:SI 1 "register_operand" "r"))] - "TARGET_H8300H || TARGET_H8300S" + "" "mov.b\\t%w1,%x0" [(set_attr "length" "2")]) @@ -3227,7 +2783,7 @@ (const_int 8)) (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") (const_int 8)))] - "TARGET_H8300H || TARGET_H8300S" + "" "mov.b\\t%x1,%x0" [(set_attr "length" "2")]) @@ -3238,7 +2794,7 @@ (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r") (const_int 8) (const_int 8)))] - "TARGET_H8300H || TARGET_H8300S" + "" "@ mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0" @@ -3250,7 +2806,7 @@ (zero_extract:SI (match_operand:SI 1 "register_operand" "r") (const_int 8) (const_int 16)))] - "TARGET_H8300H || TARGET_H8300S" + "" "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0" [(set_attr "cc" "set_znv") (set_attr "length" "6")]) @@ -3273,7 +2829,7 @@ (zero_extract:SI (match_operand:SI 1 "register_operand" "0") (const_int 8) (const_int 23)))] - "(TARGET_H8300H || TARGET_H8300S)" + "" "#" "&& reload_completed" [(parallel [(set (match_dup 0) @@ -3295,7 +2851,7 @@ (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0") (const_int 15)) (const_int 2147450880)))] - "(TARGET_H8300H || TARGET_H8300S)" + "" "#" "&& reload_completed" [(parallel [(set (match_dup 0) @@ -3316,10 +2872,9 @@ (match_operand:QI 2 "const_int_operand" "S,n")) (match_operand:SI 3 "const_int_operand" "n,n"))) (clobber (match_scratch:QI 4 "=X,&r"))] - "(TARGET_H8300H || TARGET_H8300S) - && INTVAL (operands[2]) <= 15 - && UINTVAL (operands[3]) == ((HOST_WIDE_INT_M1U << INTVAL (operands[2])) - & 0xffff)" + "INTVAL (operands[2]) <= 15 + && UINTVAL (operands[3]) == ((HOST_WIDE_INT_M1U << INTVAL (operands[2])) + & 0xffff)" "#" "&& reload_completed" [(parallel [(set (match_dup 5) @@ -3339,9 +2894,8 @@ (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "const_int_operand" "n")) (match_operand:SI 3 "single_one_operand" "n")))] - "(TARGET_H8300H || TARGET_H8300S) - && exact_log2 (INTVAL (operands[3])) < 16 - && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31" + "exact_log2 (INTVAL (operands[3])) < 16 + && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31" { operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3]))); return "shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0"; @@ -3353,7 +2907,7 @@ (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") (const_int 9)) (const_int 4194304)))] - "TARGET_H8300H || TARGET_H8300S" + "" "#" "&& reload_completed" [(set (match_dup 0) @@ -3373,7 +2927,7 @@ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") (const_int 65536)) (match_operand:SI 2 "register_operand" "0")))] - "TARGET_H8300H || TARGET_H8300S" + "" "add.w\\t%f1,%e0" [(set_attr "length" "2")]) @@ -3382,7 +2936,7 @@ (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") (const_int 16)) (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))] - "TARGET_H8300H || TARGET_H8300S" + "" "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0" [(set_attr "length" "6")]) @@ -3391,7 +2945,7 @@ (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r") (const_int 1)) (match_operand:SI 2 "register_operand" "0")))] - "TARGET_H8300H || TARGET_H8300S" + "" "#" "&& reload_completed" [(set (cc0) (compare (zero_extract:SI (match_dup 1) @@ -3416,7 +2970,7 @@ (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r")) (const_int 1)) (match_operand:SI 2 "register_operand" "0")))] - "TARGET_H8300H || TARGET_H8300S" + "" "#" "&& reload_completed" [(set (cc0) (compare (zero_extract:SI (match_dup 1) @@ -3463,7 +3017,7 @@ (match_operator:SI 1 "iorxor_operator" [(zero_extend:SI (match_operand:HI 2 "register_operand" "r")) (match_operand:SI 3 "register_operand" "0")]))] - "TARGET_H8300H || TARGET_H8300S" + "" "%c1.w\\t%T2,%f0" [(set_attr "length" "2")]) @@ -3473,7 +3027,7 @@ [(ashift:SI (match_operand:SI 2 "register_operand" "r") (const_int 16)) (match_operand:SI 3 "register_operand" "0")]))] - "TARGET_H8300H || TARGET_H8300S" + "" "%c1.w\\t%f2,%e0" [(set_attr "length" "2")]) @@ -3483,7 +3037,7 @@ [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r") (const_int 16)) (match_operand:SI 3 "register_operand" "0")]))] - "TARGET_H8300H || TARGET_H8300S" + "" "%c1.w\\t%e2,%f0" [(set_attr "length" "2")]) @@ -3530,9 +3084,8 @@ (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "")) (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0) (const_int 8))))] - "(TARGET_H8300H || TARGET_H8300S) - && reload_completed - && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))" + "reload_completed + && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))" [(set (match_dup 0) (match_dup 3))] { @@ -3546,7 +3099,7 @@ (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0")) (ashift:SI (match_operand:SI 2 "register_operand" "r") (const_int 16))))] - "TARGET_H8300H || TARGET_H8300S" + "" "mov.w\\t%f2,%e0" [(set_attr "length" "2")]) @@ -3556,7 +3109,7 @@ (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0) (const_int 8)) (const_int 65280))))] - "TARGET_H8300H || TARGET_H8300S" + "" "#" "&& reload_completed" [(set (match_dup 3) @@ -3575,7 +3128,7 @@ (const_int -65536)) (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") (const_int 16))))] - "TARGET_H8300H || TARGET_H8300S" + "" "mov.w\\t%e2,%f0" [(set_attr "length" "2")]) @@ -3584,7 +3137,7 @@ (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0")) (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r")) (const_int 8))))] - "TARGET_H8300H || TARGET_H8300S" + "" "#" "&& reload_completed" [(set (match_dup 3) @@ -3603,7 +3156,7 @@ (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0") (const_int -256)) (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))] - "TARGET_H8300H || TARGET_H8300S" + "" "mov.b\\t%X2,%w0" [(set_attr "length" "2,8")]) @@ -3612,7 +3165,7 @@ (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") (const_int 31)) (match_operand:SI 2 "register_operand" "0")))] - "TARGET_H8300H || TARGET_H8300S" + "" "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0" [(set_attr "length" "6") (set_attr "cc" "set_znv")]) @@ -3623,8 +3176,7 @@ (match_operand:SI 2 "const_int_operand" "n")) (match_operand:SI 3 "single_one_operand" "n")) (match_operand:SI 4 "register_operand" "0")))] - "(TARGET_H8300H || TARGET_H8300S) - && (INTVAL (operands[3]) & ~0xffff) == 0" + "(INTVAL (operands[3]) & ~0xffff) == 0" { rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3])) - INTVAL (operands[2])); @@ -3641,8 +3193,7 @@ (match_operand:SI 2 "const_int_operand" "n")) (match_operand:SI 3 "single_one_operand" "n")) (match_operand:SI 4 "register_operand" "0")))] - "(TARGET_H8300H || TARGET_H8300S) - && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0" + "((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0" { rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3])) + INTVAL (operands[2])); @@ -3659,7 +3210,7 @@ (const_int 1) (match_operand:SI 2 "const_int_operand" "n")) (match_operand:SI 3 "register_operand" "0")))] - "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16" + "INTVAL (operands[2]) < 16" "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0" [(set_attr "length" "6")]) @@ -3669,7 +3220,7 @@ (const_int 30)) (const_int 2)) (match_operand:SI 2 "register_operand" "0")))] - "TARGET_H8300H || TARGET_H8300S" + "" "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0" [(set_attr "length" "8")]) @@ -3680,7 +3231,7 @@ (const_int 4194304)) (match_operand:SI 2 "register_operand" "0"))) (clobber (match_scratch:HI 3 "=&r"))] - "TARGET_H8300H || TARGET_H8300S" + "" { if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) return "shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0"; @@ -3697,7 +3248,7 @@ (const_int 23)) (match_operand:SI 2 "register_operand" "0"))) (clobber (match_scratch:SI 3 "=&r"))] - "TARGET_H8300H || TARGET_H8300S" + "" "#") (define_split @@ -3706,10 +3257,9 @@ (const_int 23)) (match_dup 0))) (clobber (match_operand:SI 2 "register_operand" ""))] - "(TARGET_H8300H || TARGET_H8300S) - && epilogue_completed - && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) - && REGNO (operands[0]) != REGNO (operands[1])" + "epilogue_completed + && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) + && REGNO (operands[0]) != REGNO (operands[1])" [(parallel [(set (match_dup 3) (ashift:HI (match_dup 3) (const_int 7))) @@ -3728,10 +3278,9 @@ (const_int 23)) (match_dup 0))) (clobber (match_operand:SI 2 "register_operand" ""))] - "(TARGET_H8300H || TARGET_H8300S) - && epilogue_completed - && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1])) - && REGNO (operands[0]) != REGNO (operands[1]))" + "epilogue_completed + && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1])) + && REGNO (operands[0]) != REGNO (operands[1]))" [(set (match_dup 2) (match_dup 1)) (parallel [(set (match_dup 3) @@ -3752,7 +3301,7 @@ (const_int 1)) (lshiftrt:SI (match_dup 1) (const_int 1))))] - "TARGET_H8300H || TARGET_H8300S" + "" "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0" [(set_attr "length" "6")]) @@ -3762,7 +3311,7 @@ (const_int 16)) (ashift:SI (match_operand:SI 2 "register_operand" "r") (const_int 24))))] - "TARGET_H8300H || TARGET_H8300S" + "" "#" "&& reload_completed" [(set (match_dup 3) @@ -3785,7 +3334,7 @@ (const_int 16711680)) (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0) (const_int 24))))] - "TARGET_H8300H || TARGET_H8300S" + "" "#" "&& reload_completed" [(set (match_dup 3) @@ -3808,7 +3357,7 @@ (const_int 8388608)) (match_operand:SI 2 "register_operand" "0"))) (clobber (match_scratch:SI 3 "=&r"))] - "TARGET_H8300H || TARGET_H8300S" + "" "#") (define_split @@ -3817,10 +3366,9 @@ (const_int 8388608)) (match_dup 0))) (clobber (match_operand:SI 2 "register_operand" ""))] - "(TARGET_H8300H || TARGET_H8300S) - && epilogue_completed - && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) - && REGNO (operands[0]) != REGNO (operands[1])" + "epilogue_completed + && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) + && REGNO (operands[0]) != REGNO (operands[1])" [(parallel [(set (match_dup 3) (ashift:HI (match_dup 3) (const_int 7))) @@ -3839,10 +3387,9 @@ (const_int 8388608)) (match_dup 0))) (clobber (match_operand:SI 2 "register_operand" ""))] - "(TARGET_H8300H || TARGET_H8300S) - && epilogue_completed - && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1])) - && REGNO (operands[0]) != REGNO (operands[1]))" + "epilogue_completed + && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1])) + && REGNO (operands[0]) != REGNO (operands[1]))" [(set (match_dup 2) (match_dup 1)) (parallel [(set (match_dup 3) @@ -3863,7 +3410,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0")) (const_int 7)))] - "TARGET_H8300H || TARGET_H8300S" + "" "#" "&& reload_completed" [(parallel [(set (match_dup 2) @@ -3907,7 +3454,7 @@ (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") (const_int 16)) 3)) (clobber (match_scratch:SI 2 "=&r"))] - "TARGET_H8300H || TARGET_H8300S" + "" "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0" [(set_attr "cc" "set_znv") (set_attr "length" "10")]) @@ -3917,7 +3464,7 @@ (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") (const_int 24)) 3)) (clobber (match_scratch:SI 2 "=&r"))] - "TARGET_H8300H || TARGET_H8300S" + "" "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0" [(set_attr "cc" "set_znv") (set_attr "length" "10")]) @@ -4269,11 +3816,10 @@ (set (match_dup 0) (plus:SI (match_dup 0) (match_operand:SI 2 "register_operand" "")))] - "(TARGET_H8300H || TARGET_H8300S) - && REG_P (operands[0]) && REG_P (operands[2]) - && REGNO (operands[0]) != REGNO (operands[2]) - && (satisfies_constraint_L (operands[1]) - || satisfies_constraint_N (operands[1]))" + "REG_P (operands[0]) && REG_P (operands[2]) + && REGNO (operands[0]) != REGNO (operands[2]) + && (satisfies_constraint_L (operands[1]) + || satisfies_constraint_N (operands[1]))" [(set (match_dup 0) (match_dup 2)) (set (match_dup 0) @@ -4298,16 +3844,15 @@ (set (match_dup 0) (plus:SI (match_dup 0) (match_operand:SI 2 "const_int_operand" "")))] - "(TARGET_H8300H || TARGET_H8300S) - && operands[0] != stack_pointer_rtx - && REG_P (operands[0]) && REG_P (operands[1]) - && REGNO (operands[0]) != REGNO (operands[1]) - && !satisfies_constraint_L (operands[2]) - && !satisfies_constraint_N (operands[2]) - && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2]) - || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2]) - || INTVAL (operands[2]) == 0xffff - || INTVAL (operands[2]) == 0xfffe)" + "operands[0] != stack_pointer_rtx + && REG_P (operands[0]) && REG_P (operands[1]) + && REGNO (operands[0]) != REGNO (operands[1]) + && !satisfies_constraint_L (operands[2]) + && !satisfies_constraint_N (operands[2]) + && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2]) + || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2]) + || INTVAL (operands[2]) == 0xffff + || INTVAL (operands[2]) == 0xfffe)" [(set (match_dup 0) (match_dup 2)) (set (match_dup 0) @@ -4337,7 +3882,7 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] - "TARGET_H8300H || TARGET_H8300S" + "" [(set (match_operand:HI 0 "register_operand" "") (unspec:HI [(match_dup 0) (match_dup 1)] @@ -4363,7 +3908,7 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] - "TARGET_H8300H || TARGET_H8300S" + "" [(set (match_operand:SI 0 "register_operand" "") (unspec:SI [(match_dup 0) (match_dup 1)] @@ -4388,7 +3933,7 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] - "TARGET_H8300H || TARGET_H8300S" + "" [(set (cc0) (compare (match_dup 0) (const_int 0))) (set (pc) @@ -4418,9 +3963,8 @@ (set (match_operand:SI 2 "register_operand" "") (and:SI (match_dup 2) (const_int 255)))] - "(TARGET_H8300H || TARGET_H8300S) - && !reg_overlap_mentioned_p (operands[2], operands[1]) - && REGNO (operands[0]) == REGNO (operands[2])" + "!reg_overlap_mentioned_p (operands[2], operands[1]) + && REGNO (operands[0]) == REGNO (operands[2])" [(set (match_dup 2) (const_int 0)) (set (strict_low_part (match_dup 0)) @@ -4433,10 +3977,9 @@ (set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))] - "(TARGET_H8300H || TARGET_H8300S) - && !reg_overlap_mentioned_p (operands[0], operands[1]) - && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1])) - && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))" + "!reg_overlap_mentioned_p (operands[0], operands[1]) + && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1])) + && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))" [(set (match_dup 0) (const_int 0)) (set (strict_low_part (match_dup 2)) @@ -4452,19 +3995,18 @@ (set (match_operand:SI 2 "register_operand" "") (and:SI (match_dup 2) (match_operand:SI 3 "const_int_qi_operand" "")))] - "(TARGET_H8300H || TARGET_H8300S) - && (GET_MODE (operands[0]) == QImode - || GET_MODE (operands[0]) == HImode - || GET_MODE (operands[0]) == SImode) - && GET_MODE (operands[0]) == GET_MODE (operands[1]) - && REGNO (operands[0]) == REGNO (operands[2]) - && !reg_overlap_mentioned_p (operands[2], operands[1]) - && !(GET_MODE (operands[1]) != QImode - && GET_CODE (operands[1]) == MEM - && !offsettable_memref_p (operands[1])) - && !(GET_MODE (operands[1]) != QImode - && GET_CODE (operands[1]) == MEM - && MEM_VOLATILE_P (operands[1]))" + "(GET_MODE (operands[0]) == QImode + || GET_MODE (operands[0]) == HImode + || GET_MODE (operands[0]) == SImode) + && GET_MODE (operands[0]) == GET_MODE (operands[1]) + && REGNO (operands[0]) == REGNO (operands[2]) + && !reg_overlap_mentioned_p (operands[2], operands[1]) + && !(GET_MODE (operands[1]) != QImode + && GET_CODE (operands[1]) == MEM + && !offsettable_memref_p (operands[1])) + && !(GET_MODE (operands[1]) != QImode + && GET_CODE (operands[1]) == MEM + && MEM_VOLATILE_P (operands[1]))" [(set (match_dup 2) (const_int 0)) (set (strict_low_part (match_dup 4)) @@ -4484,8 +4026,7 @@ (set (match_dup 0) (and:SI (match_dup 0) (const_int 65280)))] - "(TARGET_H8300H || TARGET_H8300S) - && !reg_overlap_mentioned_p (operands[0], operands[1])" + "!reg_overlap_mentioned_p (operands[0], operands[1])" [(set (match_dup 0) (const_int 0)) (set (zero_extract:SI (match_dup 0) @@ -4504,11 +4045,10 @@ (set (match_dup 0) (and:SI (match_dup 0) (match_operand:SI 2 "const_int_operand" "")))] - "(TARGET_H8300H || TARGET_H8300S) - && !MEM_VOLATILE_P (operands[1]) - && offsettable_memref_p (operands[1]) - && (INTVAL (operands[2]) & ~0xffff) == 0 - && INTVAL (operands[2]) != 255" + "!MEM_VOLATILE_P (operands[1]) + && offsettable_memref_p (operands[1]) + && (INTVAL (operands[2]) & ~0xffff) == 0 + && INTVAL (operands[2]) != 255" [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) @@ -4538,7 +4078,7 @@ (set (cc0) (compare (match_operand:HI 0 "memory_operand" "") (const_int 0)))] - "TARGET_H8300H || TARGET_H8300S" + "" [(set (match_dup 1) (match_dup 0)) (set (cc0) (compare (match_dup 1) @@ -4550,7 +4090,7 @@ (set (cc0) (compare (match_operand:SI 0 "memory_operand" "") (const_int 0)))] - "TARGET_H8300H || TARGET_H8300S" + "" [(set (match_dup 1) (match_dup 0)) (set (cc0) (compare (match_dup 1) @@ -4598,9 +4138,7 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] - "(TARGET_H8300H || TARGET_H8300S) - && INTVAL (operands[1]) != 0 - && peep2_reg_dead_p (1, operands[0])" + "INTVAL (operands[1]) != 0 && peep2_reg_dead_p (1, operands[0])" [(set (match_dup 0) (unspec:HI [(match_dup 0) (match_dup 4)] @@ -4634,10 +4172,9 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] - "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && (INTVAL (operands[1]) == 1 - || (TARGET_H8300S && INTVAL (operands[1]) == 3))" + "peep2_reg_dead_p (1, operands[0]) + && (INTVAL (operands[1]) == 1 + || (TARGET_H8300S && INTVAL (operands[1]) == 3))" [(parallel [(set (match_dup 0) (ashiftrt:HI (match_dup 0) (match_dup 4))) @@ -4671,10 +4208,9 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] - "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && (INTVAL (operands[1]) == 1 - || (TARGET_H8300S && INTVAL (operands[1]) == 3))" + "peep2_reg_dead_p (1, operands[0]) + && (INTVAL (operands[1]) == 1 + || (TARGET_H8300S && INTVAL (operands[1]) == 3))" [(parallel [(set (match_dup 0) (ashiftrt:HI (match_dup 0) (match_dup 4))) @@ -4710,7 +4246,7 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] - "TARGET_H8300H || TARGET_H8300S" + "" [(set (cc0) (compare (and:HI (match_dup 0) (const_int -256)) (const_int 0))) @@ -4739,7 +4275,7 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] - "TARGET_H8300H || TARGET_H8300S" + "" [(set (cc0) (compare (and:HI (match_dup 0) (const_int -256)) (const_int 0))) @@ -4833,9 +4369,7 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] - "(TARGET_H8300H || TARGET_H8300S) - && INTVAL (operands[1]) != 0 - && peep2_reg_dead_p (1, operands[0])" + "INTVAL (operands[1]) != 0 && peep2_reg_dead_p (1, operands[0])" [(set (match_dup 0) (unspec:SI [(match_dup 0) (match_dup 4)] @@ -4869,12 +4403,11 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] - "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && (INTVAL (operands[1]) == -131072 - || INTVAL (operands[1]) == -65536 - || INTVAL (operands[1]) == 65536 - || INTVAL (operands[1]) == 131072)" + "peep2_reg_dead_p (1, operands[0]) + && (INTVAL (operands[1]) == -131072 + || INTVAL (operands[1]) == -65536 + || INTVAL (operands[1]) == 65536 + || INTVAL (operands[1]) == 131072)" [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4))) @@ -4908,14 +4441,13 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] - "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1]) - || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1]) - || INTVAL (operands[1]) == 0x0000ffff) - && INTVAL (operands[1]) != 0 - && INTVAL (operands[1]) != 1 - && INTVAL (operands[1]) != 2" + "peep2_reg_dead_p (1, operands[0]) + && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1]) + || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1]) + || INTVAL (operands[1]) == 0x0000ffff) + && INTVAL (operands[1]) != 0 + && INTVAL (operands[1]) != 1 + && INTVAL (operands[1]) != 2" [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1))) @@ -4947,12 +4479,11 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] - "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && ((INTVAL (operands[1]) | 0x00ff) == -1 - || (INTVAL (operands[1]) | 0xff00) == -1) - && INTVAL (operands[1]) != -1 - && INTVAL (operands[1]) != -2" + "peep2_reg_dead_p (1, operands[0]) + && ((INTVAL (operands[1]) | 0x00ff) == -1 + || (INTVAL (operands[1]) | 0xff00) == -1) + && INTVAL (operands[1]) != -1 + && INTVAL (operands[1]) != -2" [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4))) @@ -4988,10 +4519,9 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] - "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && (INTVAL (operands[1]) == -2147483647 - 1 - || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))" + "peep2_reg_dead_p (1, operands[0]) + && (INTVAL (operands[1]) == -2147483647 - 1 + || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))" [(set (match_dup 0) (rotate:SI (match_dup 0) (match_dup 4))) @@ -5033,11 +4563,10 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] - "(TARGET_H8300H || TARGET_H8300S) - && !peep2_reg_dead_p (1, operands[0]) - && (INTVAL (operands[1]) == 1 - || (TARGET_H8300S && INTVAL (operands[1]) == 3)) - && !same_cmp_preceding_p (insn)" + "!peep2_reg_dead_p (1, operands[0]) + && (INTVAL (operands[1]) == 1 + || (TARGET_H8300S && INTVAL (operands[1]) == 3)) + && !same_cmp_preceding_p (insn)" [(set (match_dup 4) (match_dup 0)) (parallel [(set (match_dup 4) @@ -5078,11 +4607,10 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] - "(TARGET_H8300H || TARGET_H8300S) - && !peep2_reg_dead_p (1, operands[0]) - && (INTVAL (operands[1]) == 1 - || (TARGET_H8300S && INTVAL (operands[1]) == 3)) - && !same_cmp_preceding_p (insn)" + "!peep2_reg_dead_p (1, operands[0]) + && (INTVAL (operands[1]) == 1 + || (TARGET_H8300S && INTVAL (operands[1]) == 3)) + && !same_cmp_preceding_p (insn)" [(set (match_dup 4) (match_dup 0)) (parallel [(set (match_dup 4) @@ -5120,10 +4648,9 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] - "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && (INTVAL (operands[1]) == 1 - || (TARGET_H8300S && INTVAL (operands[1]) == 3))" + "peep2_reg_dead_p (1, operands[0]) + && (INTVAL (operands[1]) == 1 + || (TARGET_H8300S && INTVAL (operands[1]) == 3))" [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 4))) @@ -5157,10 +4684,9 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] - "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && (INTVAL (operands[1]) == 1 - || (TARGET_H8300S && INTVAL (operands[1]) == 3))" + "peep2_reg_dead_p (1, operands[0]) + && (INTVAL (operands[1]) == 1 + || (TARGET_H8300S && INTVAL (operands[1]) == 3))" [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 4))) @@ -5197,15 +4723,14 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] - "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && (INTVAL (operands[1]) == 3 - || INTVAL (operands[1]) == 7 - || INTVAL (operands[1]) == 15 - || INTVAL (operands[1]) == 31 - || INTVAL (operands[1]) == 63 - || INTVAL (operands[1]) == 127 - || INTVAL (operands[1]) == 255)" + "peep2_reg_dead_p (1, operands[0]) + && (INTVAL (operands[1]) == 3 + || INTVAL (operands[1]) == 7 + || INTVAL (operands[1]) == 15 + || INTVAL (operands[1]) == 31 + || INTVAL (operands[1]) == 63 + || INTVAL (operands[1]) == 127 + || INTVAL (operands[1]) == 255)" [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 4))) @@ -5239,15 +4764,14 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] - "(TARGET_H8300H || TARGET_H8300S) - && peep2_reg_dead_p (1, operands[0]) - && ((TARGET_H8300H && INTVAL (operands[1]) == 3) - || INTVAL (operands[1]) == 7 - || INTVAL (operands[1]) == 15 - || INTVAL (operands[1]) == 31 - || INTVAL (operands[1]) == 63 - || INTVAL (operands[1]) == 127 - || INTVAL (operands[1]) == 255)" + "peep2_reg_dead_p (1, operands[0]) + && ((TARGET_H8300H && INTVAL (operands[1]) == 3) + || INTVAL (operands[1]) == 7 + || INTVAL (operands[1]) == 15 + || INTVAL (operands[1]) == 31 + || INTVAL (operands[1]) == 63 + || INTVAL (operands[1]) == 127 + || INTVAL (operands[1]) == 255)" [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 4))) @@ -5282,7 +4806,7 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] - "TARGET_H8300H || TARGET_H8300S" + "" [(set (cc0) (compare (and:SI (match_dup 0) (const_int -65536)) (const_int 0))) @@ -5311,7 +4835,7 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] - "TARGET_H8300H || TARGET_H8300S" + "" [(set (cc0) (compare (and:SI (match_dup 0) (const_int -65536)) (const_int 0))) @@ -5348,10 +4872,9 @@ [(cc0) (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] - "(TARGET_H8300H || TARGET_H8300S) - && INTVAL (operands[1]) != 0 - && !peep2_reg_dead_p (1, operands[0]) - && !same_cmp_following_p (insn)" + "INTVAL (operands[1]) != 0 + && !peep2_reg_dead_p (1, operands[0]) + && !same_cmp_following_p (insn)" [(set (match_dup 4) (match_dup 0)) (set (match_dup 4) @@ -5415,8 +4938,7 @@ (const_int -4))) (set (mem:SI (reg:SI SP_REG)) (match_operand:SI 0 "register_operand" ""))] - "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE - && REGNO (operands[0]) != SP_REG" + "!TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG" [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))] "") @@ -5432,8 +4954,7 @@ (const_int -12))) (set (mem:SI (reg:SI SP_REG)) (match_operand:SI 0 "register_operand" ""))] - "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE - && REGNO (operands[0]) != SP_REG" + "!TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG" [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4))) |