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| author | Richard Sandiford <richard.sandiford@linaro.org> | 2017-08-31 09:51:40 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2017-08-31 09:51:40 +0000 |
| commit | fca7d0a4fdd5a107429f3424600cfcb24b068bac (patch) | |
| tree | 0f7e727646b7d001f5297fc0d4c5a4dea6988b75 /gcc/config/aarch64/iterators.md | |
| parent | 3aebc597181a97c7b064f04d8e8aa30f79c51451 (diff) | |
| download | gcc-fca7d0a4fdd5a107429f3424600cfcb24b068bac.zip gcc-fca7d0a4fdd5a107429f3424600cfcb24b068bac.tar.gz gcc-fca7d0a4fdd5a107429f3424600cfcb24b068bac.tar.bz2 | |
[AArch64] Remove use of wider vector modes
The AArch64 port defined x2, x3 and x4 vector modes that were only used
in the rtl for the AdvSIMD LD{2,3,4} patterns. It seems unlikely that
this rtl would have led to any valid simplifications, since the values
involved were unspecs that had a different number of operands from the
non-dreg versions. (The dreg UNSPEC_LD2 had a single operand, while
the qreg one had two operands.)
As it happened, the patterns led to invalid simplifications on big-
endian targets due to a mix-up in the operand order, see Tamar's fix
in r240271.
This patch therefore replaces the rtl patterns with dedicated unspecs.
This allows the x2, x3 and x4 modes to be removed, avoiding a clash
with 256-bit and 512-bit SVE.
2017-08-22 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64-modes.def: Remove 32-, 48- and 64-byte
vector modes.
* config/aarch64/iterators.md (VRL2, VRL3, VRL4): Delete.
* config/aarch64/aarch64.md (UNSPEC_LD2_DREG, UNSPEC_LD3_DREG)
(UNSPEC_LD4_DREG): New unspecs.
* config/aarch64/aarch64-simd.md (aarch64_ld2<mode>_dreg_le)
(aarch64_ld2<mode>_dreg_be): Replace with...
(aarch64_ld2<mode>_dreg): ...this pattern and use the new DREG
unspec.
(aarch64_ld3<mode>_dreg_le)
(aarch64_ld3<mode>_dreg_be): Replace with...
(aarch64_ld3<mode>_dreg): ...this pattern and use the new DREG
unspec.
(aarch64_ld4<mode>_dreg_le)
(aarch64_ld4<mode>_dreg_be): Replace with...
(aarch64_ld4<mode>_dreg): ...this pattern and use the new DREG
unspec.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r251555
Diffstat (limited to 'gcc/config/aarch64/iterators.md')
| -rw-r--r-- | gcc/config/aarch64/iterators.md | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index cceb5752..c8cb54f 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -711,21 +711,6 @@ ;; ld..._lane and st..._lane operations. (define_mode_attr nregs [(OI "2") (CI "3") (XI "4")]) -(define_mode_attr VRL2 [(V8QI "V32QI") (V4HI "V16HI") - (V4HF "V16HF") - (V2SI "V8SI") (V2SF "V8SF") - (DI "V4DI") (DF "V4DF")]) - -(define_mode_attr VRL3 [(V8QI "V48QI") (V4HI "V24HI") - (V4HF "V24HF") - (V2SI "V12SI") (V2SF "V12SF") - (DI "V6DI") (DF "V6DF")]) - -(define_mode_attr VRL4 [(V8QI "V64QI") (V4HI "V32HI") - (V4HF "V32HF") - (V2SI "V16SI") (V2SF "V16SF") - (DI "V8DI") (DF "V8DF")]) - ;; Mode for atomic operation suffixes (define_mode_attr atomic_sfx [(QI "b") (HI "h") (SI "") (DI "")]) |