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| author | Jiong Wang <jiong.wang@arm.com> | 2016-07-25 16:10:52 +0000 |
|---|---|---|
| committer | Jiong Wang <jiwang@gcc.gnu.org> | 2016-07-25 16:10:52 +0000 |
| commit | 68ad28c34a53456625df599035f7b6530b46ba0f (patch) | |
| tree | 4d1eafbc0356ae5bca773c9f5624465c5d8cc307 /gcc/config/aarch64/iterators.md | |
| parent | d7f33f07d88984cbe769047e3d07fc21067fbba9 (diff) | |
| download | gcc-68ad28c34a53456625df599035f7b6530b46ba0f.zip gcc-68ad28c34a53456625df599035f7b6530b46ba0f.tar.gz gcc-68ad28c34a53456625df599035f7b6530b46ba0f.tar.bz2 | |
[AArch64][8/10] ARMv8.2-A FP16 two operands scalar intrinsics
gcc/
* config/aarch64/aarch64-simd-builtins.def: Register new builtins.
* config/aarch64/aarch64.md (<FCVT_F2FIXED:fcvt_fixed_insn>hf<mode>3):
New.
(<FCVT_FIXED2F:fcvt_fixed_insn><mode>hf3): Likewise.
(add<mode>3): Likewise.
(sub<mode>3): Likewise.
(mul<mode>3): Likewise.
(div<mode>3): Likewise.
(*div<mode>3): Likewise.
(<fmaxmin><mode>3): Extend to HF.
* config/aarch64/aarch64-simd.md (aarch64_rsqrts<mode>): Likewise.
(fabd<mode>3): Likewise.
(<FCVT_F2FIXED:fcvt_fixed_insn><VHSDF_HSDF:mode>3): Likewise.
(<FCVT_FIXED2F:fcvt_fixed_insn><VHSDI_HSDI:mode>3): Likewise.
(aarch64_fmulx<mode>): Likewise.
(aarch64_fac<optab><mode>): Likewise.
(aarch64_frecps<mode>): Likewise.
(<FCVT_F2FIXED:fcvt_fixed_insn>hfhi3): New.
(<FCVT_FIXED2F:fcvt_fixed_insn>hihf3): Likewise.
* config/aarch64/iterators.md (VHSDF_SDF): Delete.
(VSDQ_HSDI): Support HI.
(fcvt_target, FCVT_TARGET): Likewise.
* config/aarch64/arm_fp16.h (vaddh_f16, vsubh_f16, vabdh_f16,
vcageh_f16, vcagth_f16, vcaleh_f16, vcalth_f16, vceqh_f16, vcgeh_f16,
vcgth_f16, vcleh_f16, vclth_f16, vcvth_n_f16_s16, vcvth_n_f16_s32,
vcvth_n_f16_s64, vcvth_n_f16_u16, vcvth_n_f16_u32, vcvth_n_f16_u64,
vcvth_n_s16_f16, vcvth_n_s32_f16, vcvth_n_s64_f16, vcvth_n_u16_f16,
vcvth_n_u32_f16, vcvth_n_u64_f16, vdivh_f16, vmaxh_f16, vmaxnmh_f16,
vminh_f16, vminnmh_f16, vmulh_f16, vmulxh_f16, vrecpsh_f16,
vrsqrtsh_f16): New.
From-SVN: r238723
Diffstat (limited to 'gcc/config/aarch64/iterators.md')
| -rw-r--r-- | gcc/config/aarch64/iterators.md | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 20d0f1b..91e2e64 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -105,9 +105,6 @@ (define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST") (V8HF "TARGET_SIMD_F16INST") V2SF V4SF V2DF DF]) -(define_mode_iterator VHSDF_SDF [(V4HF "TARGET_SIMD_F16INST") - (V8HF "TARGET_SIMD_F16INST") - V2SF V4SF V2DF SF DF]) (define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST") (V8HF "TARGET_SIMD_F16INST") V2SF V4SF V2DF @@ -190,7 +187,9 @@ ;; Scalar and Vector modes for S and D, Vector modes for H. (define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST") (V8HI "TARGET_SIMD_F16INST") - V2SI V4SI V2DI SI DI]) + V2SI V4SI V2DI + (HI "TARGET_SIMD_F16INST") + SI DI]) ;; Vector modes for Q and H types. (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI]) @@ -705,12 +704,12 @@ (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf") (SF "si") (DF "di") (SI "sf") (DI "df") (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf") - (V8HI "v8hf")]) + (V8HI "v8hf") (HF "hi") (HI "hf")]) (define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI") (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF") (SF "SI") (DF "DI") (SI "SF") (DI "DF") (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF") - (V8HI "V8HF")]) + (V8HI "V8HF") (HF "HI") (HI "HF")]) ;; for the inequal width integer to fp conversions |