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| author | Richard Sandiford <richard.sandiford@arm.com> | 2024-11-11 12:32:19 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2024-11-11 12:32:19 +0000 |
| commit | ddc014d2c69240ecf8a49399d1a58ebb2530b9d1 (patch) | |
| tree | 0fb3c5ee4624f72a003911c7cbd4db3163b8e54a /gcc/config.gcc | |
| parent | fdbe94f7c88f53f1d65e9891e6eab2fe803a6e77 (diff) | |
| download | gcc-ddc014d2c69240ecf8a49399d1a58ebb2530b9d1.zip gcc-ddc014d2c69240ecf8a49399d1a58ebb2530b9d1.tar.gz gcc-ddc014d2c69240ecf8a49399d1a58ebb2530b9d1.tar.bz2 | |
aarch64: Define arm_neon.h types in arm_sve.h too
This patch moves the scalar and single-vector Advanced SIMD types
from arm_neon.h into a private header, so that they can be defined
by arm_sve.h as well. This is needed for the upcoming SVE2.1
hybrid-VLA reductions, which return 128-bit Advanced SIMD vectors.
The approach follows Claudio's patch for FP8.
gcc/
* config.gcc (extra_headers): Add arm_private_neon_types.h.
* config/aarch64/arm_private_neon_types.h: New file, split out
from...
* config/aarch64/arm_neon.h: ...here.
* config/aarch64/arm_sve.h: Include arm_private_neon_types.h
Diffstat (limited to 'gcc/config.gcc')
| -rw-r--r-- | gcc/config.gcc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config.gcc b/gcc/config.gcc index b813352..9b616bd 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -347,7 +347,7 @@ m32c*-*-*) ;; aarch64*-*-*) cpu_type=aarch64 - extra_headers="arm_fp16.h arm_neon.h arm_bf16.h arm_acle.h arm_sve.h arm_sme.h arm_neon_sve_bridge.h arm_private_fp8.h" + extra_headers="arm_fp16.h arm_neon.h arm_bf16.h arm_acle.h arm_sve.h arm_sme.h arm_neon_sve_bridge.h arm_private_fp8.h arm_private_neon_types.h" c_target_objs="aarch64-c.o" cxx_target_objs="aarch64-c.o" d_target_objs="aarch64-d.o" |