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authorPan Li <pan2.li@intel.com>2025-03-03 14:51:21 +0800
committerPan Li <pan2.li@intel.com>2025-03-04 09:38:59 +0800
commitbfb9276f344cbc6794379d61d0279dfc3a7441b3 (patch)
treec6baaa4f175093eae6e1ed951192e3346456a72a /gcc/ada/a-intnam-unixware.ads
parent491c0b8071323295471648a438eb4c216d15735c (diff)
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RISC-V: Fix the test case bug-3.c failureHEADtrunkmaster
The bug-3.c would like to check the slli a[0-9]+, a[0-9]+, 33 for the big poly int handling. But the underlying insn may change to slli 1 + slli 32 with sorts of optimization. Thus, update the asm check to function body check with above slli 1 + slli 32 series. The below test suites are passed for this patch. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/bug-3.c: Update asm check to function body check. Signed-off-by: Pan Li <pan2.li@intel.com>
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