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| author | Dongyan Chen <chendongyan@isrc.iscas.ac.cn> | 2025-05-07 11:33:06 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2025-05-07 11:33:41 -0600 |
| commit | 974b079741f902fcf4323dfcecbbffdb9f56f3bf (patch) | |
| tree | 4da6bdb3b50a5b865c6d07a5eadfc6ebfdf6ed44 /gcc | |
| parent | fe10ca6e3cf583640155812b230a0153ce4dc7b7 (diff) | |
| download | gcc-trunk.zip gcc-trunk.tar.gz gcc-trunk.tar.bz2 | |
This patch support zama16b extension[1].
To enable GCC to recognize and process zama16b extension correctly at compile time.
[1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New extension.
* config/riscv/riscv.opt: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-48.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/common/config/riscv/riscv-common.cc | 2 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.opt | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/arch-48.c | 5 |
3 files changed, 9 insertions, 0 deletions
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 0233e1a..ca14eb9 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -327,6 +327,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0}, {"zabha", ISA_SPEC_CLASS_NONE, 1, 0}, {"zacas", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zama16b", ISA_SPEC_CLASS_NONE, 1, 0}, {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbb", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1657,6 +1658,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = RISCV_EXT_FLAG_ENTRY ("zalrsc", x_riscv_za_subext, MASK_ZALRSC), RISCV_EXT_FLAG_ENTRY ("zabha", x_riscv_za_subext, MASK_ZABHA), RISCV_EXT_FLAG_ENTRY ("zacas", x_riscv_za_subext, MASK_ZACAS), + RISCV_EXT_FLAG_ENTRY ("zama16b", x_riscv_za_subext, MASK_ZAMA16B), RISCV_EXT_FLAG_ENTRY ("zba", x_riscv_zb_subext, MASK_ZBA), RISCV_EXT_FLAG_ENTRY ("zbb", x_riscv_zb_subext, MASK_ZBB), diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 9e471be..80593ee 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -274,6 +274,8 @@ Mask(ZA64RS) Var(riscv_za_subext) Mask(ZA128RS) Var(riscv_za_subext) +Mask(ZAMA16B) Var(riscv_za_subext) + TargetVariable int riscv_zb_subext diff --git a/gcc/testsuite/gcc.target/riscv/arch-48.c b/gcc/testsuite/gcc.target/riscv/arch-48.c new file mode 100644 index 0000000..58a558e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-48.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zama16b -mabi=lp64" } */ +int foo() +{ +} |