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| author | Richard Sandiford <richard.sandiford@arm.com> | 2019-12-10 16:46:05 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2019-12-10 16:46:05 +0000 |
| commit | aa1a27950ae6a41a5a75f5d05eccb52bb31e240c (patch) | |
| tree | 2c7f15e37418b7b4d02415a81e042a338b5a7f13 /depcomp | |
| parent | 30f8bf3d6c072a8fce14e8a003dff485a9068a97 (diff) | |
| download | gcc-aa1a27950ae6a41a5a75f5d05eccb52bb31e240c.zip gcc-aa1a27950ae6a41a5a75f5d05eccb52bb31e240c.tar.gz gcc-aa1a27950ae6a41a5a75f5d05eccb52bb31e240c.tar.bz2 | |
[AArch64] Don't allow partial SVE modes in GPRs
With -msve-vector-bits=N, the payload of some partial SVE modes can
be 16 bytes or smaller, which makes them small enough to fit in a
pair of GPRs. We specifically don't want that, because the payload
is distributed evenly across the SVE register rather than collected
at one end. Marshalling it into a GPR via register operations would
be expensive.
2019-12-10 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Don't
allow SVE modes in GPRs.
gcc/testsuite/
* gcc.target/aarch64/sve/mixed_size_7.c: New test.
From-SVN: r279174
Diffstat (limited to 'depcomp')
0 files changed, 0 insertions, 0 deletions