diff options
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 4 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/mixed_size_7.c | 28 |
4 files changed, 40 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 577acb1..f848de6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2019-12-10 Richard Sandiford <richard.sandiford@arm.com> + * config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Don't + allow SVE modes in GPRs. + +2019-12-10 Richard Sandiford <richard.sandiford@arm.com> + * config/aarch64/iterators.md (vccore): New iterator. * config/aarch64/aarch64-sve.md (vec_series<mode>): Use it instead of vwcore. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index a3b18b3..b0aca03 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -2019,9 +2019,11 @@ aarch64_hard_regno_mode_ok (unsigned regno, machine_mode mode) if (GP_REGNUM_P (regno)) { + if (vec_flags & VEC_ANY_SVE) + return false; if (known_le (GET_MODE_SIZE (mode), 8)) return true; - else if (known_le (GET_MODE_SIZE (mode), 16)) + if (known_le (GET_MODE_SIZE (mode), 16)) return (regno & 1) == 0; } else if (FP_REGNUM_P (regno)) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index c1f22f2c..4e52f2a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2019-12-10 Richard Sandiford <richard.sandiford@arm.com> + * gcc.target/aarch64/sve/mixed_size_7.c: New test. + +2019-12-10 Richard Sandiford <richard.sandiford@arm.com> + * gcc.target/aarch64/sve/mixed_size_6.c: New test. 2019-12-10 Frederik Harwath <frederik@codesourcery.com> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/mixed_size_7.c b/gcc/testsuite/gcc.target/aarch64/sve/mixed_size_7.c new file mode 100644 index 0000000..3a403c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/mixed_size_7.c @@ -0,0 +1,28 @@ +/* Originally gcc.dg/vect/bb-slp-6.c */ +/* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=256 -fno-vect-cost-model" } */ + +#define N 16 + +unsigned int out[N]; +unsigned int in[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; + +__attribute__ ((noinline)) int +main1 (unsigned int x, unsigned int y) +{ + int i; + unsigned int *pin = &in[0]; + unsigned int *pout = &out[0]; + unsigned int a0, a1, a2, a3; + + a0 = *pin++ + 23; + a1 = *pin++ + 142; + a2 = *pin++ + 2; + a3 = *pin++ + 31; + + *pout++ = a0 * x; + *pout++ = a1 * y; + *pout++ = a2 * x; + *pout++ = a3 * y; + + return 0; +} |