[RISC-V] Expose sign extension for 32 bit rotates by constant values on rv64

Trivial improvement for 32 bit rotates on rv64 that I noticed while looking at
a PR121778.  We were failing to use the _extended variant when the rotation
count was a constant on rv64 after cobbling together a prototype match.pd
pattern.

I suspect the guard was added by Jivan to avoid having to muck around in the
thead bitmanip extensions.  But that's a bit of speculation on my part.

I reviewed the thead extensions and they do the expected thing for the W form
rotate.  So this patch adds a pattern to thead.md that exposes the sign
extension and removes the restriction on generating that form from bitmanip.md.

I can envision this will help something, somewhere, but it's generally going to
be very much on the margins.  I didn't take the time to find/construct a
testcase showing the missed optimization.  There is one test that triggers the
thead W form rotate (xtheadbb-srri.c), so that's got some coverage and passes
(and I verified it's using the version with the sign extension exposed, so
that's good).  PR121778 will trigger the missed optimization if we add a
suitable match.pd.

Regression tested on riscv32-elf and riscv64-elf.  Bootstraps on the BPI and
Pioneer are in flight, but won't be finished for a long time.

Obviously waiting on pre-commit CI before moving forward.

	* config/riscv/bitmanip.md (rotrsi3): Use the sign extended form
	for 32 bit rotates on TARGET_64BIT, even for constant counts.
	* config/riscv/thead.md (th_srrisi3_extended): New pattern.
	(th_srri<mode>3): Adjust formatting.

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