diff options
| -rw-r--r-- | gcc/config/riscv/bitmanip.md | 2 | ||||
| -rw-r--r-- | gcc/config/riscv/thead.md | 18 |
2 files changed, 18 insertions, 2 deletions
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 697198f..166ddd9 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -357,7 +357,7 @@ { if (TARGET_XTHEADBB && !immediate_operand (operands[2], VOIDmode)) FAIL; - if (TARGET_64BIT && register_operand (operands[2], QImode)) + if (TARGET_64BIT) { rtx t = gen_reg_rtx (DImode); emit_insn (gen_rotrsi3_sext (t, operands[1], operands[2])); diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index 20e82e6..42171a5 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -34,7 +34,7 @@ (define_insn "*th_srri<mode>3" [(set (match_operand:GPR 0 "register_operand" "=r") (rotatert:GPR (match_operand:GPR 1 "register_operand" "r") - (match_operand 2 "const_int_operand" "n")))] + (match_operand 2 "const_int_operand" "n")))] "TARGET_XTHEADBB && (TARGET_64BIT || <MODE>mode == SImode)" { bool wform = TARGET_64BIT && (<MODE>mode == SImode); @@ -45,6 +45,22 @@ [(set_attr "type" "bitmanip") (set_attr "mode" "<GPR:MODE>")]) +;; Version with explicit sign extension to facilitate sign extension +;; removal. +(define_insn "*th_srrisi3_extended" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (rotatert:SI (match_operand:SI 1 "register_operand" "r") + (match_operand 2 "const_int_operand" "n"))))] + "TARGET_XTHEADBB && TARGET_64BIT" + { + operands[2] = GEN_INT (INTVAL (operands[2]) + & (GET_MODE_BITSIZE (SImode) - 1)); + return "th.srriw\t%0,%1,%2"; + } + [(set_attr "type" "bitmanip") + (set_attr "mode" "SI")]) + (define_insn "*th_ext<mode>4" [(set (match_operand:GPR 0 "register_operand" "=r") (sign_extract:GPR (match_operand:GPR 1 "register_operand" "r") |