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author | James Greenhalgh <james.greenhalgh@arm.com> | 2013-04-29 10:51:46 +0000 |
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committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2013-04-29 10:51:46 +0000 |
commit | ce9668243743907c0115948d8b080162620fc1a9 (patch) | |
tree | 74a80df816bbb8772b95160f65f1897606216fb6 | |
parent | b9de24febe601ae0ad27642a1d8dae84bf58065c (diff) | |
download | gcc-ce9668243743907c0115948d8b080162620fc1a9.zip gcc-ce9668243743907c0115948d8b080162620fc1a9.tar.gz gcc-ce9668243743907c0115948d8b080162620fc1a9.tar.bz2 |
[AArch64] Map fcvt intrinsics to builtin name directly.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): Use new names for
fcvt builtins.
* config/aarch64/aarch64-simd-builtins.def (fcvtzs): Split as...
(lbtruncv2sf, lbtruncv4sf, lbtruncv2df): ...This.
(fcvtzu): Split as...
(lbtruncuv2sf, lbtruncuv4sf, lbtruncuv2df): ...This.
(fcvtas): Split as...
(lroundv2sf, lroundv4sf, lroundv2df, lroundsf, lrounddf): ...This.
(fcvtau): Split as...
(lrounduv2sf, lrounduv4sf, lrounduv2df, lroundusf, lroundudf): ...This.
(fcvtps): Split as...
(lceilv2sf, lceilv4sf, lceilv2df): ...This.
(fcvtpu): Split as...
(lceiluv2sf, lceiluv4sf, lceiluv2df, lceilusf, lceiludf): ...This.
(fcvtms): Split as...
(lfloorv2sf, lfloorv4sf, lfloorv2df): ...This.
(fcvtmu): Split as...
(lflooruv2sf, lflooruv4sf, lflooruv2df, lfloorusf, lfloorudf): ...This.
(lfrintnv2sf, lfrintnv4sf, lfrintnv2df, lfrintnsf, lfrintndf): New.
(lfrintnuv2sf, lfrintnuv4sf, lfrintnuv2df): Likewise.
(lfrintnusf, lfrintnudf): Likewise.
* config/aarch64/aarch64-simd.md
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Convert to
define_insn.
(aarch64_fcvt<frint_suffix><su><mode>): Remove.
* config/aarch64/iterators.md (FCVT): Include UNSPEC_FRINTN.
(fcvt_pattern): Likewise.
From-SVN: r198398
-rw-r--r-- | gcc/ChangeLog | 31 | ||||
-rw-r--r-- | gcc/config/aarch64/aarch64-builtins.c | 28 | ||||
-rw-r--r-- | gcc/config/aarch64/aarch64-simd-builtins.def | 62 | ||||
-rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 14 | ||||
-rw-r--r-- | gcc/config/aarch64/iterators.md | 5 |
5 files changed, 116 insertions, 24 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 38467e7..d095797 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,36 @@ 2013-04-29 James Greenhalgh <james.greenhalgh@arm.com> + * config/aarch64/aarch64-builtins.c + (aarch64_builtin_vectorized_function): Use new names for + fcvt builtins. + * config/aarch64/aarch64-simd-builtins.def (fcvtzs): Split as... + (lbtruncv2sf, lbtruncv4sf, lbtruncv2df): ...This. + (fcvtzu): Split as... + (lbtruncuv2sf, lbtruncuv4sf, lbtruncuv2df): ...This. + (fcvtas): Split as... + (lroundv2sf, lroundv4sf, lroundv2df, lroundsf, lrounddf): ...This. + (fcvtau): Split as... + (lrounduv2sf, lrounduv4sf, lrounduv2df, lroundusf, lroundudf): ...This. + (fcvtps): Split as... + (lceilv2sf, lceilv4sf, lceilv2df): ...This. + (fcvtpu): Split as... + (lceiluv2sf, lceiluv4sf, lceiluv2df, lceilusf, lceiludf): ...This. + (fcvtms): Split as... + (lfloorv2sf, lfloorv4sf, lfloorv2df): ...This. + (fcvtmu): Split as... + (lflooruv2sf, lflooruv4sf, lflooruv2df, lfloorusf, lfloorudf): ...This. + (lfrintnv2sf, lfrintnv4sf, lfrintnv2df, lfrintnsf, lfrintndf): New. + (lfrintnuv2sf, lfrintnuv4sf, lfrintnuv2df): Likewise. + (lfrintnusf, lfrintnudf): Likewise. + * config/aarch64/aarch64-simd.md + (l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Convert to + define_insn. + (aarch64_fcvt<frint_suffix><su><mode>): Remove. + * config/aarch64/iterators.md (FCVT): Include UNSPEC_FRINTN. + (fcvt_pattern): Likewise. + +2013-04-29 James Greenhalgh <james.greenhalgh@arm.com> + * config/aarch64/aarch64-simd.md (l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Rename to... (l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2): ... This. diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index 08bfe01..f540568 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -1245,9 +1245,33 @@ aarch64_builtin_vectorized_function (tree fndecl, tree type_out, tree type_in) (out_mode == N##Imode && out_n == C \ && in_mode == N##Fmode && in_n == C) case BUILT_IN_LFLOOR: - return AARCH64_FIND_FRINT_VARIANT (fcvtms); + { + tree new_tree = NULL_TREE; + if (AARCH64_CHECK_BUILTIN_MODE (2, D)) + new_tree = + aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_lfloorv2dfv2di]; + else if (AARCH64_CHECK_BUILTIN_MODE (4, S)) + new_tree = + aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_lfloorv4sfv4si]; + else if (AARCH64_CHECK_BUILTIN_MODE (2, S)) + new_tree = + aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_lfloorv2sfv2si]; + return new_tree; + } case BUILT_IN_LCEIL: - return AARCH64_FIND_FRINT_VARIANT (fcvtps); + { + tree new_tree = NULL_TREE; + if (AARCH64_CHECK_BUILTIN_MODE (2, D)) + new_tree = + aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_lceilv2dfv2di]; + else if (AARCH64_CHECK_BUILTIN_MODE (4, S)) + new_tree = + aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_lceilv4sfv4si]; + else if (AARCH64_CHECK_BUILTIN_MODE (2, S)) + new_tree = + aarch64_builtin_decls[AARCH64_SIMD_BUILTIN_lceilv2sfv2si]; + return new_tree; + } default: return NULL_TREE; } diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 6b41466..745b36a 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -256,15 +256,59 @@ BUILTIN_VDQF (UNOP, round, 2) BUILTIN_VDQF (UNOP, frintn, 2) - /* Implemented by aarch64_fcvt<frint_suffix><su><mode>. */ - BUILTIN_VDQF (UNOP, fcvtzs, 0) - BUILTIN_VDQF (UNOP, fcvtzu, 0) - BUILTIN_VDQF (UNOP, fcvtas, 0) - BUILTIN_VDQF (UNOP, fcvtau, 0) - BUILTIN_VDQF (UNOP, fcvtps, 0) - BUILTIN_VDQF (UNOP, fcvtpu, 0) - BUILTIN_VDQF (UNOP, fcvtms, 0) - BUILTIN_VDQF (UNOP, fcvtmu, 0) + /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2. */ + VAR1 (UNOP, lbtruncv2sf, 2, v2si) + VAR1 (UNOP, lbtruncv4sf, 2, v4si) + VAR1 (UNOP, lbtruncv2df, 2, v2di) + + VAR1 (UNOP, lbtruncuv2sf, 2, v2si) + VAR1 (UNOP, lbtruncuv4sf, 2, v4si) + VAR1 (UNOP, lbtruncuv2df, 2, v2di) + + VAR1 (UNOP, lroundv2sf, 2, v2si) + VAR1 (UNOP, lroundv4sf, 2, v4si) + VAR1 (UNOP, lroundv2df, 2, v2di) + /* Implemented by l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2. */ + VAR1 (UNOP, lroundsf, 2, si) + VAR1 (UNOP, lrounddf, 2, di) + + VAR1 (UNOP, lrounduv2sf, 2, v2si) + VAR1 (UNOP, lrounduv4sf, 2, v4si) + VAR1 (UNOP, lrounduv2df, 2, v2di) + VAR1 (UNOP, lroundusf, 2, si) + VAR1 (UNOP, lroundudf, 2, di) + + VAR1 (UNOP, lceilv2sf, 2, v2si) + VAR1 (UNOP, lceilv4sf, 2, v4si) + VAR1 (UNOP, lceilv2df, 2, v2di) + + VAR1 (UNOP, lceiluv2sf, 2, v2si) + VAR1 (UNOP, lceiluv4sf, 2, v4si) + VAR1 (UNOP, lceiluv2df, 2, v2di) + VAR1 (UNOP, lceilusf, 2, si) + VAR1 (UNOP, lceiludf, 2, di) + + VAR1 (UNOP, lfloorv2sf, 2, v2si) + VAR1 (UNOP, lfloorv4sf, 2, v4si) + VAR1 (UNOP, lfloorv2df, 2, v2di) + + VAR1 (UNOP, lflooruv2sf, 2, v2si) + VAR1 (UNOP, lflooruv4sf, 2, v4si) + VAR1 (UNOP, lflooruv2df, 2, v2di) + VAR1 (UNOP, lfloorusf, 2, si) + VAR1 (UNOP, lfloorudf, 2, di) + + VAR1 (UNOP, lfrintnv2sf, 2, v2si) + VAR1 (UNOP, lfrintnv4sf, 2, v4si) + VAR1 (UNOP, lfrintnv2df, 2, v2di) + VAR1 (UNOP, lfrintnsf, 2, si) + VAR1 (UNOP, lfrintndf, 2, di) + + VAR1 (UNOP, lfrintnuv2sf, 2, v2si) + VAR1 (UNOP, lfrintnuv4sf, 2, v4si) + VAR1 (UNOP, lfrintnuv2df, 2, v2di) + VAR1 (UNOP, lfrintnusf, 2, si) + VAR1 (UNOP, lfrintnudf, 2, di) /* Implemented by aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>. */ diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index b716fbe..4c678ba 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1244,7 +1244,9 @@ (set_attr "simd_mode" "<MODE>")] ) -(define_insn "aarch64_fcvt<frint_suffix><su><mode>" +;; Vector versions of the fcvt standard patterns. +;; Expands to lbtrunc, lround, lceil, lfloor +(define_insn "l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2" [(set (match_operand:<FCVT_TARGET> 0 "register_operand" "=w") (FIXUORS:<FCVT_TARGET> (unspec:<FCVT_TARGET> [(match_operand:VDQF 1 "register_operand" "w")] @@ -1255,16 +1257,6 @@ (set_attr "simd_mode" "<MODE>")] ) -;; Vector versions of the fcvt standard patterns. -;; Expands to lbtrunc, lround, lceil, lfloor -(define_expand "l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2" - [(set (match_operand:<FCVT_TARGET> 0 "register_operand") - (FIXUORS:<FCVT_TARGET> (unspec:<FCVT_TARGET> - [(match_operand:VDQF 1 "register_operand")] - FCVT)))] - "TARGET_SIMD" - {}) - (define_insn "aarch64_vmls<mode>" [(set (match_operand:VDQF 0 "register_operand" "=w") (minus:VDQF (match_operand:VDQF 1 "register_operand" "0") diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index a2ad866..5c769f8 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -696,7 +696,7 @@ UNSPEC_FRINTA]) (define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM - UNSPEC_FRINTA]) + UNSPEC_FRINTA UNSPEC_FRINTN]) (define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX]) @@ -798,7 +798,8 @@ (UNSPEC_FRINTN "n")]) (define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round") - (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")]) + (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor") + (UNSPEC_FRINTN "frintn")]) (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip") (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn") |