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| author | James Greenhalgh <james.greenhalgh@arm.com> | 2013-04-29 10:48:54 +0000 |
|---|---|---|
| committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2013-04-29 10:48:54 +0000 |
| commit | b9de24febe601ae0ad27642a1d8dae84bf58065c (patch) | |
| tree | 82f6b369a05ea280e0d7d80d2bd74ea21060b9ac | |
| parent | 77a205be4eac302ab5abda34f181fd11cc64cda8 (diff) | |
| download | gcc-b9de24febe601ae0ad27642a1d8dae84bf58065c.zip gcc-b9de24febe601ae0ad27642a1d8dae84bf58065c.tar.gz gcc-b9de24febe601ae0ad27642a1d8dae84bf58065c.tar.bz2 | |
[AArch64] Fix order of modes to lroundmn2 standard names.
gcc/
* config/aarch64/aarch64-simd.md
(l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Rename to...
(l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2): ... This.
From-SVN: r198397
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 2 |
2 files changed, 7 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a46324a..38467e7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2013-04-29 James Greenhalgh <james.greenhalgh@arm.com> + * config/aarch64/aarch64-simd.md + (l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2): Rename to... + (l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2): ... This. + +2013-04-29 James Greenhalgh <james.greenhalgh@arm.com> + * config/aarch64/arm_neon.h (vrndq<a,m,n,p>_f<32, 64>): Rename to... (vrnd<a,m,n,p>q_f<32, 64>): ...This, implement using builtin. (vrnd<a,m,n,p>_f32): Implement using builtins. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 5f14cc6..b716fbe 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1257,7 +1257,7 @@ ;; Vector versions of the fcvt standard patterns. ;; Expands to lbtrunc, lround, lceil, lfloor -(define_expand "l<fcvt_pattern><su_optab><fcvt_target><VDQF:mode>2" +(define_expand "l<fcvt_pattern><su_optab><VDQF:mode><fcvt_target>2" [(set (match_operand:<FCVT_TARGET> 0 "register_operand") (FIXUORS:<FCVT_TARGET> (unspec:<FCVT_TARGET> [(match_operand:VDQF 1 "register_operand")] |