diff options
| author | Kito Cheng <kito.cheng@sifive.com> | 2022-12-19 17:28:25 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2022-12-19 17:39:33 +0800 |
| commit | b346e77f4d7b482df78f119819b1e06a544ef515 (patch) | |
| tree | 21c3821d832d39f8e7a950c7b58ddd8bbde4a71e | |
| parent | 97a8e88cd7d22562c0ea4f73687d3c93c21e12fb (diff) | |
| download | gcc-b346e77f4d7b482df78f119819b1e06a544ef515.zip gcc-b346e77f4d7b482df78f119819b1e06a544ef515.tar.gz gcc-b346e77f4d7b482df78f119819b1e06a544ef515.tar.bz2 | |
RISC-V: Fix vwrite_csr.c and vread_csr.c
gcc/testsuite:
* gcc.target/riscv/rvv/base/vread_csr.c: Use specific option
instead.
* gcc.target/riscv/rvv/base/vwrite_csr.c: Ditto.
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c | 3 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c | 3 |
2 files changed, 2 insertions, 4 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c index 69c9c1f..ac5484f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O3" } */ -/* { dg-skip-if "test intrinsic using rvv" { *-*-* } { "*" } { "-march=rv*v*zfh*" } } */ +/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c index f9b4e88..830ddb9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O3" } */ -/* { dg-skip-if "test intrinsic using rvv" { *-*-* } { "*" } { "-march=rv*v*zfh*" } } */ +/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */ #include "riscv_vector.h" |