From b346e77f4d7b482df78f119819b1e06a544ef515 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Mon, 19 Dec 2022 17:28:25 +0800 Subject: RISC-V: Fix vwrite_csr.c and vread_csr.c gcc/testsuite: * gcc.target/riscv/rvv/base/vread_csr.c: Use specific option instead. * gcc.target/riscv/rvv/base/vwrite_csr.c: Ditto. --- gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c | 3 +-- gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c index 69c9c1f..ac5484f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O3" } */ -/* { dg-skip-if "test intrinsic using rvv" { *-*-* } { "*" } { "-march=rv*v*zfh*" } } */ +/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c index f9b4e88..830ddb9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c @@ -1,6 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-O3" } */ -/* { dg-skip-if "test intrinsic using rvv" { *-*-* } { "*" } { "-march=rv*v*zfh*" } } */ +/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */ #include "riscv_vector.h" -- cgit v1.1