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author | James Greenhalgh <james.greenhalgh@arm.com> | 2013-04-29 10:54:32 +0000 |
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committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2013-04-29 10:54:32 +0000 |
commit | 1709ff9b5c53b13140819feae5e381fac22f6416 (patch) | |
tree | 248a658f62189c70f42826531f9b262a7eca21b0 | |
parent | ce9668243743907c0115948d8b080162620fc1a9 (diff) | |
download | gcc-1709ff9b5c53b13140819feae5e381fac22f6416.zip gcc-1709ff9b5c53b13140819feae5e381fac22f6416.tar.gz gcc-1709ff9b5c53b13140819feae5e381fac22f6416.tar.bz2 |
[AArch64] Add vector int to float conversions.
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_fold_builtin): Fold float conversions.
* config/aarch64/aarch64-simd-builtins.def
(floatv2si, floatv4si, floatv2di): New.
(floatunsv2si, floatunsv4si, floatunsv2di): Likewise.
* config/aarch64/aarch64-simd.md
(<optab><fcvt_target><VDQF:mode>2): New, expands to float and floatuns.
* config/aarch64/iterators.md (FLOATUORS): New.
(optab): Add float, floatuns.
(su_optab): Likewise.
From-SVN: r198399
-rw-r--r-- | gcc/ChangeLog | 13 | ||||
-rw-r--r-- | gcc/config/aarch64/aarch64-builtins.c | 5 | ||||
-rw-r--r-- | gcc/config/aarch64/aarch64-simd-builtins.def | 9 | ||||
-rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 10 | ||||
-rw-r--r-- | gcc/config/aarch64/iterators.md | 6 |
5 files changed, 43 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d095797..2e21471 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,19 @@ 2013-04-29 James Greenhalgh <james.greenhalgh@arm.com> * config/aarch64/aarch64-builtins.c + (aarch64_fold_builtin): Fold float conversions. + * config/aarch64/aarch64-simd-builtins.def + (floatv2si, floatv4si, floatv2di): New. + (floatunsv2si, floatunsv4si, floatunsv2di): Likewise. + * config/aarch64/aarch64-simd.md + (<optab><fcvt_target><VDQF:mode>2): New, expands to float and floatuns. + * config/aarch64/iterators.md (FLOATUORS): New. + (optab): Add float, floatuns. + (su_optab): Likewise. + +2013-04-29 James Greenhalgh <james.greenhalgh@arm.com> + + * config/aarch64/aarch64-builtins.c (aarch64_builtin_vectorized_function): Use new names for fcvt builtins. * config/aarch64/aarch64-simd-builtins.def (fcvtzs): Split as... diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index f540568..d2e5136 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -1296,6 +1296,11 @@ aarch64_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *args, BUILTIN_VDQF (UNOP, abs, 2) return fold_build1 (ABS_EXPR, type, args[0]); break; + VAR1 (UNOP, floatv2si, 2, v2sf) + VAR1 (UNOP, floatv4si, 2, v4sf) + VAR1 (UNOP, floatv2di, 2, v2df) + return fold_build1 (FLOAT_EXPR, type, args[0]); + break; default: break; } diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 745b36a..8df3dac 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -310,6 +310,15 @@ VAR1 (UNOP, lfrintnusf, 2, si) VAR1 (UNOP, lfrintnudf, 2, di) + /* Implemented by <optab><fcvt_target><VDQF:mode>2. */ + VAR1 (UNOP, floatv2si, 2, v2sf) + VAR1 (UNOP, floatv4si, 2, v4sf) + VAR1 (UNOP, floatv2di, 2, v2df) + + VAR1 (UNOP, floatunsv2si, 2, v2sf) + VAR1 (UNOP, floatunsv4si, 2, v4sf) + VAR1 (UNOP, floatunsv2di, 2, v2df) + /* Implemented by aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>. */ BUILTIN_VALL (BINOP, zip1, 0) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 4c678ba..067c849 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1257,6 +1257,16 @@ (set_attr "simd_mode" "<MODE>")] ) +(define_insn "<optab><fcvt_target><VDQF:mode>2" + [(set (match_operand:VDQF 0 "register_operand" "=w") + (FLOATUORS:VDQF + (match_operand:<FCVT_TARGET> 1 "register_operand" "w")))] + "TARGET_SIMD" + "<su_optab>cvtf\\t%0.<Vtype>, %1.<Vtype>" + [(set_attr "simd_type" "simd_icvtf") + (set_attr "simd_mode" "<MODE>")] +) + (define_insn "aarch64_vmls<mode>" [(set (match_operand:VDQF 0 "register_operand" "=w") (minus:VDQF (match_operand:VDQF 1 "register_operand" "0") diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 5c769f8..8668d3f 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -530,6 +530,9 @@ ;; Iterator for integer conversions (define_code_iterator FIXUORS [fix unsigned_fix]) +;; Iterator for float conversions +(define_code_iterator FLOATUORS [float unsigned_float]) + ;; Code iterator for variants of vector max and min. (define_code_iterator MAXMIN [smax smin umax umin]) @@ -557,6 +560,8 @@ (zero_extend "zero_extend") (sign_extract "extv") (zero_extract "extzv") + (float "float") + (unsigned_float "floatuns") (and "and") (ior "ior") (xor "xor") @@ -579,6 +584,7 @@ (define_code_attr su_optab [(sign_extend "") (zero_extend "u") (div "") (udiv "u") (fix "") (unsigned_fix "u") + (float "s") (unsigned_float "u") (ss_plus "s") (us_plus "u") (ss_minus "s") (us_minus "u")]) |