Age | Commit message (Expand) | Author | Files | Lines |
2019-06-13 | opcodes/or1k: Regenerate opcodes | Stafford Horne | 9 | -273/+1195 |
2019-06-12 | Add missing ChangeLog entries | Peter Bergner | 1 | -0/+4 |
2019-06-12 | Remove the ldmx mnemonic that never made it into POWER9. | Peter Bergner | 1 | -2/+0 |
2019-06-05 | i386: Check vector length for EVEX vextractfXX and vinsertfXX | H.J. Lu | 3 | -9/+92 |
2019-06-04 | i386: Check for reserved VEX.vvvv and EVEX.vvvv | H.J. Lu | 2 | -10/+27 |
2019-06-04 | Enable Intel AVX512_VP2INTERSECT insn | H.J. Lu | 8 | -4142/+4240 |
2019-06-04 | Add support for Intel ENQCMD[S] instructions | H.J. Lu | 7 | -4064/+4190 |
2019-06-04 | Remove an unnecessary set of parentheses in the arm-dis.c source file. | Alan Hayward | 2 | -1/+5 |
2019-06-03 | Don't waste space in prefix_opcd_indices | Alan Modra | 2 | -1/+5 |
2019-05-28 | x86: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVL | H.J. Lu | 3 | -4/+11 |
2019-05-24 | Regen POTFILES for bpf | Alan Modra | 2 | -0/+11 |
2019-05-24 | PowerPC D-form prefixed loads and stores | Peter Bergner | 2 | -4/+197 |
2019-05-24 | PowerPC add initial -mfuture instruction support | Peter Bergner | 3 | -1/+130 |
2019-05-23 | opcodes: add support for eBPF | Jose E. Marchesi | 14 | -3/+5837 |
2019-05-21 | [binutils, ARM] <spec_reg> changes for VMRS and VMSR instructions | Sudakshina Das | 2 | -2/+27 |
2019-05-21 | [binutils, Arm] Add support for conditional instructions in Armv8.1-M Mainline | Sudakshina Das | 2 | -0/+99 |
2019-05-21 | [binutils, Arm] Add support for shift instructions in MVE | Sudakshina Das | 2 | -0/+194 |
2019-05-21 | MIPS/gas: Reject $0 as source register for DAUI instruction | Faraz Shahbazker | 2 | -1/+6 |
2019-05-20 | Updated translations for various binutils subdirectories. | Nick Clifton | 2 | -584/+977 |
2019-05-16 | [PATCH 56/57][Arm][OBJDUMP] Add support for MVE instructions: vpnot, vpsel, v... | Andre Vieira | 2 | -0/+154 |
2019-05-16 | [PATCH 55/57][Arm][OBJDUMP] Add support for MVE instructions: vmul, vmulh, vr... | Andre Vieira | 2 | -0/+83 |
2019-05-16 | [PATCH 54/57][Arm][OBJDUMP] Add support for MVE instructions: vmax(a), vmax(a... | Andre Vieira | 2 | -0/+163 |
2019-05-16 | [PATCH 53/57][Arm][OBJDUMP] Add support for MVE instructions: vand, vbrsr, vc... | Andre Vieira | 2 | -0/+76 |
2019-05-16 | [PATCH 52/57][Arm][OBJDUMP] Add support for MVE instructions: vadc, vabav, va... | Andre Vieira | 2 | -0/+154 |
2019-05-16 | [PATCH 51/57][Arm][OBJDUMP] Add support for MVE instructions: lctp, letp, wls... | Andre Vieira | 2 | -3/+24 |
2019-05-16 | [PATCH 50/57][Arm][OBJDUMP] Add support for MVE shift instructions | Andre Vieira | 2 | -2/+422 |
2019-05-16 | [PATCH 49/57][Arm][OBJDUMP] Add support for MVE complex number instructions | Andre Vieira | 2 | -0/+152 |
2019-05-16 | [PATCH 48/57][Arm][OBJDUMP] Add support for MVE instructions: vddup, vdwdup, ... | Andre Vieira | 2 | -1/+96 |
2019-05-16 | [PATCH 47/57][Arm][OBJDUMP] Add support for MVE instructions: vaddv, vmlaldav... | Andre Vieira | 2 | -0/+298 |
2019-05-16 | [PATCH 46/57][Arm][OBJDUMP] Add support for MVE instructions: vmovl, vmull, v... | Andre Vieira | 2 | -0/+206 |
2019-05-16 | [PATCH 45/57][Arm][OBJDUMP] Add support for MVE instructions: vmov, vmvn, vor... | Andre Vieira | 2 | -5/+621 |
2019-05-16 | [PATCH 44/57][Arm][OBJDUMP] Add support for MVE instructions: vcvt and vrint | Andre Vieira | 2 | -2/+383 |
2019-05-16 | [PATCH 43/57][Arm][OBJDUMP] Add support for MVE instructions: scatter stores ... | Andre Vieira | 2 | -1/+368 |
2019-05-16 | [PATCH 42/57][Arm][OBJDUMP] Add support for MVE instructions: vldr[bhw] and v... | Andre Vieira | 2 | -0/+278 |
2019-05-16 | [PATCH 41/57][Arm][OBJDUMP] Add support for MVE instructions: vld[24] and vst... | Andre Vieira | 2 | -0/+191 |
2019-05-16 | [PATCH 40/57][Arm][OBJDUMP] Add support for MVE instructions: vdup, veor, vfm... | Andre Vieira | 2 | -14/+222 |
2019-05-16 | [PATCH 39/57][Arm][OBJDUMP] Add support for MVE instructions: vpt, vpst and vcmp | Andre Vieira | 2 | -12/+642 |
2019-05-16 | [PATCH 38/57][Arm][OBJDUMP] Disable the use of MVE reserved coproc numbers in... | Andre Vieira | 2 | -0/+12 |
2019-05-16 | [PATCH 37/57][Arm][OBJDUMP] Add framework for MVE instructions | Andre Vieira | 2 | -4/+279 |
2019-05-14 | A series of fixes to addres problems detected by compiling the assembler with... | Nick Clifton | 2 | -1/+10 |
2019-05-10 | Add macro expansions for ADD, SUB, DADD and DSUB for MIPS r6 | Faraz Shahbazker | 2 | -4/+9 |
2019-05-11 | PowerPC objdump -Mraw | Alan Modra | 2 | -3/+10 |
2019-05-09 | Update printing of optional operands during disassembly. | Peter Bergner | 1 | -9/+8 |
2019-05-09 | [binutils][aarch64] Add SVE2 instructions. | Matthew Malcomson | 3 | -941/+4569 |
2019-05-09 | [binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand. | Matthew Malcomson | 6 | -22/+41 |
2019-05-09 | [binutils][aarch64] New sve_size_tsz_bhs iclass. | Matthew Malcomson | 3 | -0/+24 |
2019-05-09 | [binutils][aarch64] New SVE_Zm4_11_INDEX operand. | Matthew Malcomson | 7 | -14/+36 |
2019-05-09 | [binutils][aarch64] New sve_shift_tsz_bhsd iclass. | Matthew Malcomson | 3 | -0/+19 |
2019-05-09 | [binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand. | Matthew Malcomson | 8 | -32/+73 |
2019-05-09 | [binutils][aarch64] New sve_size_013 iclass. | Matthew Malcomson | 3 | -0/+25 |