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2024-07-20Add markers for 2.43 branch/releaseNick Clifton1-0/+4
2024-07-19MIPS/opcodes: Replace "y" microMIPS operand code with "x"Maciej W. Rozycki1-2/+2
2024-07-19MIPS/opcodes: Mark MT thread context move assembly idioms as aliasesMaciej W. Rozycki1-38/+38
2024-07-19MIPS/opcodes: Mark PAUSE as an aliasMaciej W. Rozycki1-1/+1
2024-07-19MIPS/opcodes: Reorder coprocessor moves alphabeticallyMaciej W. Rozycki2-58/+62
2024-07-19MIPS/opcodes: Make AL a shorthand for INSN2_ALIASMaciej W. Rozycki2-56/+60
2024-07-19MIPS/opcodes: Rename the AL membership shorthand to ALXMaciej W. Rozycki1-88/+88
2024-07-19MIPS/opcodes: Remove the regular MIPS "+t" operand codeYunQiang Su1-2/+1
2024-07-19MIPS/opcodes: Output thread context registers numerically with MFTR/MTTRMaciej W. Rozycki1-2/+2
2024-07-19MIPS/opcodes: Exclude $0 from "-x" R6 operand typeMaciej W. Rozycki1-1/+1
2024-07-18opcodes: aarch64: enforce checks on subclass flags in aarch64-gen.cIndu Bhagat1-0/+19
2024-07-18opcodes: aarch64: denote subclasses for insns of iclass dp_2srcIndu Bhagat1-24/+24
2024-07-18opcodes: aarch64: add flags to denote subclasses of uncond branchesIndu Bhagat1-19/+19
2024-07-18opcodes: aarch64: add flags to denote subclasses of arithmetic insnsIndu Bhagat1-15/+15
2024-07-18opcodes: aarch64: add flags to denote subclasses of ldst insnsIndu Bhagat1-43/+43
2024-07-12aarch64: Add support for sme2.1 zero instructions.Srinath Parvathaneni3-208/+330
2024-07-12aarch64: Add support for sme2.1 movaz instructions.Srinath Parvathaneni10-283/+493
2024-07-12aarch64: Add support for sme2.1 luti2 and luti4 instructions.Srinath Parvathaneni4-210/+274
2024-07-08aarch64: Add support for sve2p1 pmov instruction.srinath6-221/+409
2024-07-08aarch64: Add support for sve2p1 tbxq instruction.Srinath Parvathaneni2-158/+170
2024-07-08aarch64: Add support for sve2p1 zipq[1-2] instructions.Srinath Parvathaneni2-160/+184
2024-07-08aarch64: Add support for sve2p1 uzpq[1-2] instructions.Srinath Parvathaneni2-151/+175
2024-07-08aarch64: Add support for sve2p1 tblq instruction.Srinath Parvathaneni2-175/+187
2024-07-08aarch64: Add support for sve2p1 orqv instruction.Srinath Parvathaneni2-152/+164
2024-07-05aarch64: add Debug Feature Register 2 (ID_AA64DFR2_EL1)Matthieu Longo1-0/+1
2024-07-05aarch64: add STEP2 feature and its associated registersMatthieu Longo1-0/+1
2024-07-05aarch64: add SPMU2 feature and its associated registersMatthieu Longo1-0/+1
2024-07-05aarch64: add E3DSE feature and its associated registersMatthieu Longo1-0/+2
2024-07-05RISC-V: avoid use of match_opcode() in riscv_insn_types[]Jan Beulich1-102/+102
2024-07-05x86: Correct position of ".s" for CCMPcc in disassemblerCui, Lili2-2/+12
2024-07-04Support APX CFCMOVCui, Lili6-2237/+3269
2024-06-28x86/APX: apply NDD-to-legacy transformation to further CMOVcc formsJan Beulich2-31/+34
2024-06-28x86/APX: extend TEST-by-imm7 optimization to CTESTccJan Beulich2-31/+31
2024-06-28x86/APX: optimize {nf}-form IMUL-by-power-of-2 to SHLJan Beulich2-12/+12
2024-06-28x86/APX: optimize certain {nf}-form insns to LEAJan Beulich2-7/+7
2024-06-28x86/APX: optimize {nf}-form rotate-by-width-less-1Jan Beulich2-15/+15
2024-06-28x86/APX: optimize {nf} forms of ADD/SUB with specific immediatesJan Beulich2-20/+20
2024-06-28RISC-V: Add Zabha extension CAS instructions.Jiawei1-0/+8
2024-06-26aarch64: FP8 scale and convert - Implement minor improvementsVictor Do Nascimento1-12/+12
2024-06-25aarch64: Treat operand Rt_IN_SYS_ALIASES as register number (PR 31919)Jens Remus1-1/+1
2024-06-25aarch64: Fix FEAT_B16B16 sve2 instruction constraints.Srinath Parvathaneni2-33/+33
2024-06-25arch64: Fix the wrong constraint used for sve2p1 instructions.Srinath Parvathaneni1-13/+12
2024-06-25aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.Srinath Parvathaneni5-209/+206
2024-06-25aarch64: Fix sve2p1 extq instruction operands.Srinath Parvathaneni5-28/+24
2024-06-25aarch64: Fix sve2p1 dupq instruction operands.Srinath Parvathaneni8-61/+13
2024-06-24aarch64: Add SME FP8 multiplication instructionsAndrew Carlotti6-834/+1345
2024-06-24aarch64: Add FP8 Neon and SVE multiplication instructionsAndrew Carlotti8-366/+877
2024-06-24gas, aarch64: Add SME2 lutv2 extensionsaurabh.jha@arm.com8-100/+208
2024-06-21x86: optimize {,V}PEXTR{D,Q} with immediate of 0Jan Beulich2-16/+16
2024-06-21x86: optimize left-shift-by-1Jan Beulich2-52/+52
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