| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2017-12-13 | Add missing RISC-V fsrmi and fsflagsi instructions. | Jim Wilson | 2 | -0/+9 |
| 2017-12-13 | This patch enables disassembler_needs_relocs for PRU. It is needed to print c... | Dimitar Dimitrov | 2 | -0/+9 |
| 2017-12-11 | [Binutils][Objdump]Check symbol section information while search a mapping sy... | Renlin Li | 2 | -3/+11 |
| 2017-12-03 | Fix "FAIL: VLE relocations 3" | Alan Modra | 2 | -7/+7 |
| 2017-12-01 | Use consistent types for holding instructions, instruction masks, etc. | Peter Bergner | 3 | -517/+556 |
| 2017-11-30 | x86: derive DispN from BaseIndex | Jan Beulich | 4 | -4142/+4196 |
| 2017-11-30 | x86: drop Vec_Disp8 | Jan Beulich | 6 | -16227/+16225 |
| 2017-11-29 | Support --localedir, --datarootdir and --datadir | Stefan Stroe | 2 | -4/+10 |
| 2017-11-27 | Update the simplified Chinese translation of the messages in the opcodes libr... | Nick Clifton | 2 | -437/+945 |
| 2017-11-24 | x86: don't omit disambiguating suffixes from "fi*" | Jan Beulich | 2 | -12/+17 |
| 2017-11-23 | Add Disp8MemShift for AVX512 VAES instructions. | Igor Tsimbalist | 3 | -24/+29 |
| 2017-11-23 | x86: fix AVX-512 16-bit addressing | Jan Beulich | 2 | -0/+7 |
| 2017-11-23 | x86: correct UDn | Jan Beulich | 4 | -14/+47 |
| 2017-11-22 | Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor. | Igor Tsimbalist | 3 | -4/+9 |
| 2017-11-22 | Update ChangeLog | Igor Tsimbalist | 1 | -0/+5 |
| 2017-11-22 | Remove Vec_Disp8 from vpcompressb and vpexpandb. | Igor Tsimbalist | 2 | -13/+12 |
| 2017-11-22 | [ARC] Fix handling of ARCv2 H-register class. | claziss | 2 | -0/+6 |
| 2017-11-21 | [ARC] Improve printing of pc-relative instructions. | claziss | 3 | -17/+52 |
| 2017-11-16 | Add new AArch64 FP16 FM{A|S} instructions. | Tamar Christina | 2 | -2/+7 |
| 2017-11-16 | Correct AArch64 crypto dependencies. | Tamar Christina | 1 | -4/+6 |
| 2017-11-16 | Add assembler and disassembler support for the new Armv8.4-a instructions for... | Tamar Christina | 3 | -2925/+3534 |
| 2017-11-16 | x86: ignore high register select bit(s) in 32- and 16-bit modes | Jan Beulich | 2 | -28/+47 |
| 2017-11-15 | x86: use correct register names | Jan Beulich | 2 | -3/+8 |
| 2017-11-15 | x86: drop VEXI4_Fixup() | Jan Beulich | 2 | -50/+45 |
| 2017-11-15 | x86-64: don't allow use of %axl as accumulator | Jan Beulich | 3 | -2/+7 |
| 2017-11-14 | x86: add disassembler support for XOP VPCOM* pseudo-ops | Jan Beulich | 2 | -8/+67 |
| 2017-11-14 | x86: add support for AVX-512 VPCMP*{B,W} pseudo-ops | Jan Beulich | 4 | -29/+1554 |
| 2017-11-14 | x86: string insns don't allow displacements | Jan Beulich | 3 | -42/+48 |
| 2017-11-13 | x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should not allow q suffix | Jan Beulich | 3 | -10/+16 |
| 2017-11-09 | Add assembler and disassembler support for the new Armv8.4-a registers for AA... | Tamar Christina | 2 | -1/+164 |
| 2017-11-09 | Add the operand encoding types for the new Armv8.2-a back-ported instructions... | Tamar Christina | 2 | -0/+97 |
| 2017-11-09 | Adds the new Fields and Operand types for the new instructions in Armv8.4-a. | Tamar Christina | 11 | -179/+296 |
| 2017-11-09 | Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options... | Tamar Christina | 2 | -0/+37 |
| 2017-11-08 | Split the AArch64 Crypto instructions for AES and SHA1+2 into their own optio... | Nick Clifton | 2 | -17/+39 |
| 2017-11-08 | Adds command line support for Armv8.4-A, via the new command line option -mar... | Jiong Wang | 2 | -0/+24 |
| 2017-11-07 | opcodes/arc: Fix incorrect insn_class for some nps insns | Andrew Burgess | 2 | -4/+8 |
| 2017-11-07 | ngettext support | Alan Modra | 2 | -16/+35 |
| 2017-11-03 | [ARC] Force the disassam to use the hexadecimal number for printing | claziss | 2 | -1/+21 |
| 2017-11-03 | [ARC] Sync opcode data base. | claziss | 3 | -1588/+3455 |
| 2017-10-25 | PR22348, conflicting global vars in crx and cr16 | Alan Modra | 4 | -20/+33 |
| 2017-10-24 | RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0 | Andrew Waterman | 2 | -7/+33 |
| 2017-10-23 | Add missing ChangeLog entries | Igor Tsimbalist | 1 | -0/+110 |
| 2017-10-23 | Fix the master due to bad regenerated files | Igor Tsimbalist | 3 | -5469/+11545 |
| 2017-10-23 | Enable Intel AVX512_BITALG instructions. | Igor Tsimbalist | 5 | -3/+51 |
| 2017-10-23 | Enable Intel AVX512_VNNI instructions. | Igor Tsimbalist | 5 | -6/+48 |
| 2017-10-23 | Enable Intel VPCLMULQDQ instruction. | Igor Tsimbalist | 5 | -14/+30 |
| 2017-10-23 | Enable Intel VAES instructions. | Igor Tsimbalist | 7 | -5576/+5902 |
| 2017-10-23 | Enable Intel GFNI instructions. | Igor Tsimbalist | 7 | -5443/+6011 |
| 2017-10-23 | Enable Intel AVX512_VBMI2 instructions. | Igor Tsimbalist | 7 | -5389/+6652 |
| 2017-10-18 | [Visium] Disassemble the operands of the stop instruction. | Eric Botcazou | 2 | -1/+5 |
