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AgeCommit message (Expand)AuthorFilesLines
2022-10-06RISC-V: Print XTheadMemPair literal as "immediate"Tsukasa OI1-1/+1
2022-10-06RISC-V: Fix T-Head immediate types on printingTsukasa OI1-4/+4
2022-10-06RISC-V: Print comma and tabs as the "text" styleTsukasa OI1-11/+20
2022-10-06RISC-V: Optimize riscv_disassemble_data printfTsukasa OI1-6/+4
2022-10-06RISC-V: Fix printf argument types corresponding %xTsukasa OI1-7/+7
2022-10-06RISC-V: Fix immediates to have "immediate" styleTsukasa OI1-5/+5
2022-10-05Arm64: support CLEARBHB aliasJan Beulich4-1576/+1579
2022-10-04RISC-V: Fix buffer overflow on print_insn_riscvTsukasa OI1-1/+1
2022-10-04RISC-V: Renamed INSN_CLASS for floating point in integer extensions.Nelson Chu1-222/+222
2022-10-04opcodes/riscv: style csr names as registersAndrew Burgess1-1/+2
2022-10-03RISC-V: Move supervisor instructions after all unprivileged onesTsukasa OI1-32/+32
2022-09-30RISC-V: Relax "fmv.[sdq]" requirementsTsukasa OI1-3/+3
2022-09-30RISC-V: fix build after "Add support for arbitrary immediate encoding formats"Jan Beulich1-2/+2
2022-09-30RISC-V: drop stray INSN_ALIAS flagsJan Beulich1-3/+3
2022-09-30RISC-V: re-arrange opcode table for consistent alias handlingJan Beulich1-38/+38
2022-09-30x86: correct build dependencies in opcodes/Jan Beulich2-12/+16
2022-09-30x86/Intel: restrict suffix derivationJan Beulich4-7481/+7463
2022-09-30PR29626, Segfault when disassembling ARM codeAlan Modra1-63/+61
2022-09-23RISC-V: Add Zawrs ISA extension supportChristoph Müllner1-0/+4
2022-09-22RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner1-0/+24
2022-09-22RISC-V: Add support for literal instruction argumentsChristoph Müllner1-0/+9
2022-09-22RISC-V: Add T-Head MemIdx vendor extensionChristoph Müllner1-0/+60
2022-09-22RISC-V: Add T-Head FMemIdx vendor extensionChristoph Müllner1-0/+10
2022-09-22RISC-V: Add T-Head MAC vendor extensionChristoph Müllner1-0/+8
2022-09-22RISC-V: Add T-Head CondMov vendor extensionChristoph Müllner1-0/+4
2022-09-22RISC-V: Add T-Head Bitmanip vendor extensionChristoph Müllner1-0/+17
2022-09-22RISC-V: Add support for arbitrary immediate encoding formatsChristoph Müllner1-0/+34
2022-09-22RISC-V: Add T-Head SYNC vendor extensionChristoph Müllner1-0/+7
2022-09-22RISC-V: Add T-Head CMO vendor extensionChristoph Müllner1-0/+25
2022-09-22opcodes: SH fix bank register disassemble.Yoshinori Sato2-0/+7
2022-09-22RISC-V: Remove "b" operand type from disassemblerTsukasa OI1-1/+0
2022-09-14bfd: Stop using -Wstack-usage=262144 when built with ClangTsukasa OI1-0/+18
2022-09-14ubsan: arm-dis.c index out of boundsAlan Modra1-1/+1
2022-09-12ppc: Document the -mfuture and -Mfuture options and make them usablePeter Bergner2-1/+3
2022-09-12x86: avoid i386_dis_printf()'s staging area for a fair part of outputJan Beulich1-20/+24
2022-09-06opcodes: Add non-enum disassembler optionsTsukasa OI3-0/+6
2022-09-02RISC-V: Print highest address (-1) on the disassemblerTsukasa OI1-6/+14
2022-09-02RISC-V: PR29342, Fix RV32 disassembler address computationTsukasa OI1-1/+7
2022-08-30RISC-V: Add 'Zmmul' extension in assembler.Tsukasa OI1-13/+13
2022-08-16i386: Add MAX_OPERAND_BUFFER_SIZEH.J. Lu1-3/+6
2022-08-16x86: shorten certain template namesJan Beulich1-26/+32
2022-08-16x86: template-ize certain vector conversion insnsJan Beulich3-181/+167
2022-08-16x86: template-ize vector packed byte/word integer insnsJan Beulich2-763/+692
2022-08-16x86: re-order AVX512 S/G templatesJan Beulich2-185/+182
2022-08-16x86: template-ize vector packed dword/qword integer insnsJan Beulich2-615/+518
2022-08-16x86: template-ize packed/scalar vector floating point insnsJan Beulich3-3577/+3345
2022-08-16revert "x86: Also pass -P to $(CPP) when processing i386-opc.tbl"Jan Beulich4-32/+56
2022-08-11ppc/svp64: support svindex instructionDmitry Selyutin1-0/+15
2022-08-11ppc/svp64: support svremap instructionDmitry Selyutin1-0/+20
2022-08-11ppc/svp64: support svshape instructionDmitry Selyutin1-0/+23
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