| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2015-09-10 | S/390: Fix instruction format of crj*, clrj*, and clgrj*. | Andreas Krebbel | 1 | -3/+3 |
| 2015-09-10 | S/390: Remove F_20 and FE_20. Adjust comments. | Andreas Krebbel | 1 | -70/+66 |
| 2015-09-10 | S/390: Fix MASK_RIE_R0PI and MASK_RIE_R0PU. | Andreas Krebbel | 1 | -2/+2 |
| 2015-09-09 | S/390: Remove trailing zeros on 4-bytes opcodes. | Andreas Krebbel | 2 | -7/+9 |
| 2015-09-09 | S/390: Fix opcode of ppno. | Andreas Krebbel | 1 | -1/+1 |
| 2015-08-25 | Support for the sparc %pmcdper privileged register. | Jose E. Marchesi | 2 | -2/+11 |
| 2015-08-24 | Fix the partial disassembly of a broken three byte instruction at the end of ... | Jan Stancek | 2 | -2/+8 |
| 2015-08-21 | PR binutils/18257: Properly decode x86/Intel mask instructions. | Alexander Fomin | 2 | -59/+450 |
| 2015-08-17 | Trailing space in opcodes/ generated files | Alan Modra | 5 | -845/+835 |
| 2015-08-13 | Fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp. | Andre Vieira | 2 | -3/+19 |
| 2015-08-12 | [MIPS] Map 'move' to 'or'. | Simon Dardis | 3 | -3/+8 |
| 2015-08-12 | Remove trailing spaces in opcodes | H.J. Lu | 137 | -4012/+4012 |
| 2015-08-11 | Fix the disassembly of the AArch64 SIMD EXT instruction. | Nick Clifton | 2 | -1/+7 |
| 2015-08-10 | Add SIGRIE instruction for MIPS R6 | Robert Suchanek | 2 | -0/+5 |
| 2015-08-07 | Remove CpuFMA4 support from CPU_ZNVER1_FLAGS. | Amit Pawar | 3 | -2/+7 |
| 2015-07-30 | Properly disassemble movnti in Intel mode | H.J. Lu | 2 | -5/+20 |
| 2015-07-27 | Regenerate configure files | H.J. Lu | 2 | -2/+6 |
| 2015-07-23 | Fix ubsan signed integer overflow | Alan Modra | 2 | -3/+8 |
| 2015-07-22 | Fix memory operand size for vcvtt?ps2u?qq instructions | H.J. Lu | 2 | -4/+13 |
| 2015-07-16 | Updates the ARM disassembler's output of floating point constants to include ... | Alessandro Marzocchi | 2 | -2/+40 |
| 2015-07-14 | Sync config/warnings.m4 with GCC | H.J. Lu | 2 | -0/+16 |
| 2015-07-10 | Add missing changelog entries | Alan Modra | 1 | -0/+4 |
| 2015-07-03 | Remove ppc860, ppc750cl, ppc7450 insns from common ppc. | Alan Modra | 3 | -5/+17 |
| 2015-07-01 | Opcodes and assembler support for Nios II R2 | Sandra Loosemore | 3 | -56/+952 |
| 2015-06-30 | Add support for monitorx/mwaitx instructions | Amit Pawar | 7 | -5301/+5462 |
| 2015-06-22 | PPC sync instruction accepts invalid and incompatible operands | Peter Bergner | 2 | -13/+48 |
| 2015-06-22 | Stop "objdump -d" from disassembling past a symbolic address. | Nick Clifton | 7 | -6/+33 |
| 2015-06-19 | Allow for optional operands with non-zero default values. | Peter Bergner | 3 | -26/+34 |
| 2015-06-16 | [AArch64] Support id_mmfr4 system register | Matthew Wahab | 2 | -0/+5 |
| 2015-06-16 | Fixes a compile time warnng about left shifting a negative value. | Szabolcs Nagy | 2 | -1/+5 |
| 2015-06-12 | Remove unused MTMSRD_L macro and re-add accidentally deleted comment. | Peter Bergner | 2 | -2/+7 |
| 2015-06-04 | Add hwsync extended mnemonic. | Peter Bergner | 1 | -0/+1 |
| 2015-06-04 | Fixes the check for emulated MSP430 instrucrtions that take no operands. | Nick Clifton | 2 | -1/+6 |
| 2015-06-02 | [ARM] Support for ARMv8.1 Adv.SIMD extension | Matthew Wahab | 1 | -0/+19 |
| 2015-06-02 | [ARM] Add support for ARMv8.1 PAN extension | Matthew Wahab | 2 | -0/+10 |
| 2015-06-02 | [ARM] Rework CPU feature selection in the disassembler | Matthew Wahab | 2 | -29/+31 |
| 2015-06-02 | [AArch64] Support for ARMv8.1a Adv.SIMD instructions | Matthew Wahab | 5 | -1249/+1359 |
| 2015-06-02 | [AArch64] Support for ARMv8.1a Limited Ordering Regions extension | Matthew Wahab | 5 | -401/+478 |
| 2015-06-01 | [AArch64][libopcode] Add support for PAN architecture extension | Matthew Wahab | 2 | -0/+46 |
| 2015-06-01 | x86/Intel: fix i386_optab[] for vcvt{,u}si2s{d,s} | Jan Beulich | 2 | -6/+10 |
| 2015-06-01 | x86/Intel: disassemble vcvt{,u}si2s{d,s} with correct operand order | Jan Beulich | 2 | -0/+12 |
| 2015-06-01 | x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s} | Jan Beulich | 3 | -0/+143 |
| 2015-05-18 | Remove Disp32 from AMD64 direct call/jmp | H.J. Lu | 3 | -4/+9 |
| 2015-05-15 | Support AMD64/Intel ISAs in assembler/disassembler | H.J. Lu | 7 | -5296/+5387 |
| 2015-05-14 | Fix some PPC assembler errors. | Peter Bergner | 2 | -3/+15 |
| 2015-05-13 | Add missing ChangeLog entries for PR binutis/18386 | H.J. Lu | 1 | -0/+13 |
| 2015-05-11 | Remove Disp16|Disp32 from 64-bit direct branches | H.J. Lu | 3 | -5/+26 |
| 2015-05-11 | Add Intel MCU support to opcodes | H.J. Lu | 8 | -5817/+5853 |
| 2015-05-09 | Ignore 0x66 prefix for call/jmp/jcc in 64-bit mode | H.J. Lu | 1 | -10/+40 |
| 2015-04-30 | Make RL78 disassembler and simulator respect ISA for mul/div | DJ Delorie | 5 | -447/+509 |
