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AgeCommit message (Expand)AuthorFilesLines
2021-03-12Re: x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Alan Modra2-1/+5
2021-03-11x86: re-order logic in OP_XMM()Jan Beulich2-35/+35
2021-03-11x86: drop a few redundant EVEX-related checksJan Beulich2-4/+10
2021-03-11x86: remove stray uses of xmmq_modeJan Beulich2-4/+6
2021-03-10x86/Intel: correct AVX512 S/G disassemblyJan Beulich6-114/+42
2021-03-10x86: re-arrange enumerator and table entry orderJan Beulich2-77/+100
2021-03-10x86: reuse further VEX entries for EVEXJan Beulich6-98/+46
2021-03-10x86: reuse VEX entries for EVEX vperm{q,pd}Jan Beulich5-22/+20
2021-03-10x86: re-arrange order of decode for various EVEX opcodesJan Beulich7-439/+249
2021-03-10x86: re-arrange order of decode for various mask reg opcodesJan Beulich2-600/+427
2021-03-10x86: re-arrange order of decode for various VEX opcodesJan Beulich2-154/+104
2021-03-10x86: re-arrange order of decode for various legacy opcodesJan Beulich2-70/+43
2021-03-10x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Jan Beulich2-48/+61
2021-03-09x86: fold some prefix related attributes into a single oneJan Beulich5-7503/+7517
2021-03-09x86-64: make SYSEXIT handling similar to SYSRET'sJan Beulich4-3/+10
2021-03-03x86: infer operand count of templatesJan Beulich3-3453/+3447
2021-02-19RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu3-32/+54
2021-02-18RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu3-95/+20
2021-02-17read_leb128 overflow checkingAlan Modra2-6/+27
2021-02-16x86: CVTPI2PD has special behaviorJan Beulich3-2/+39
2021-02-16x86: have preprocessor expand macrosJan Beulich3-11/+11
2021-02-15IBM Z: Implement instruction set extensionsAndreas Krebbel3-0/+35
2021-02-10bfd, opcodes, libctf: support --with-included-gettextNick Alcock3-2/+20
2021-02-08opcodes: tic54x: namespace exported variablesMike Frysinger3-8/+26
2021-02-04RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.Nelson Chu2-53/+10
2021-01-26Segmentation fault i386-genAlan Modra2-0/+7
2021-01-15RISC-V: Indent and GNU coding standards tidy, also aligned the code.Nelson Chu2-710/+714
2021-01-15RISC-V: Error and warning messages tidy.Nelson Chu2-1/+5
2021-01-15RISC-V: Comments tidy and improvement.Nelson Chu3-32/+34
2021-01-13Regen Makefile.in for jobserver.m4 aclocal.m4 dependencyAlan Modra2-0/+5
2021-01-12Implement a workaround for GNU mak jobserverH.J. Lu4-0/+28
2021-01-12Updated translations for some subdirectoriesNick Clifton2-237/+282
2021-01-11Binutils: Check if AR works with --plugin and rcH.J. Lu2-3/+16
2021-01-11aarch64: Remove support for CSREKyrylo Tkachov6-1433/+1433
2021-01-11Updated translations for multiple subdirectoriesNick Clifton6-1234/+1453
2021-01-09Binutils: Pass --plugin to AR and RANLIBH.J. Lu2-2/+29
2021-01-09Change version number to 2.36.50 and regenerate filesNick Clifton3-242/+288
2021-01-09Add Changelog entries and NEWS entries for 2.36 branchNick Clifton1-0/+4
2021-01-09POWER10: Add Return-Oriented Programming instructionsPeter Bergner2-1/+51
2021-01-09configure regenAlan Modra2-2/+6
2021-01-08Updated Swedish translation for the opcodes/ subdirectoryNick Clifton2-280/+353
2021-01-08Fix places in the AArch64 opcodes library code where a call to assert() has s...Nick Clifton3-7/+16
2021-01-08Treat the AArch64 register id_aa64mmfr2_el1 as a core system register.Nick Clifton2-1/+7
2021-01-07libtool.m4: update GNU/Hurd test from upstream. In upstream libtool, 47a889a...Samuel Thibault2-11/+5
2021-01-07Updated French translation for the opcodes/ subdirectory.Nick Clifton2-242/+317
2021-01-07m68k: Require m68020up rather than m68000up for CHK.L instruction.Fredrik Noring2-1/+6
2021-01-07RISC-V: Add pause hint instruction.Philipp Tomsich2-0/+7
2021-01-07RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).Claire Xenia Wolf2-4/+63
2021-01-01PR27116, Spelling errors found by Debian style checkerAlan Modra1-1/+1
2021-01-01Update year range in copyright notice of binutils filesAlan Modra276-279/+283
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