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bfd/
* elf-bfd.h (elf_symbol_from): Remove unused ABFD parameter.
* elf.c (ignore_section_sym, _bfd_elf_copy_private_symbol_data),
(swap_out_syms): Adjust elf_symbol_from invocation.
binutils/
* nm.c (print_symbol): Adjust elf_symbol_from invocation.
* objcopy.c (is_hidden_symbol): Likewise.
gas/
* config/obj-elf.c (obj_elf_visibility, elf_frob_symbol): Adjust
elf_symbol_from invocation.
* config/tc-aarch64.c (s_variant_pcs): Likewise.
* config/tc-m68hc11.c (s_m68hc11_mark_symbol): Likewise.
* config/tc-ppc.c (ppc_elf_localentry, ppc_force_relocation),
(ppc_fix_adjustable): Likewise.
* config/tc-xgate.c (xgate_frob_symbol): Likewise.
ld/
* plugin.c (asymbol_from_plugin_symbol): Adjust elf_symbol_from
invocation.
opcodes/
* ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
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disassembly of PowerPC binaries.
* ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
for hidden, local, no-type symbols.
(disassemble_init_powerpc): Point the symbol_is_valid field in the
info structure at the new function.
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opcodes/
* csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
* testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
opcode fixing.
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Add arches CK804, CK805 and CK800. CK800 is an special arch which
support all instructions for CSKYV2. Refine the cpu tables to
simplify adding a new cpu.
Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com>
gas/
* config/tc-csky.c (struct csky_cpu_info): Add new members
isa_flag, features and ver.
(struct csky_cpu_feature): New.
(struct csky_cpu_version): New.
(CSKY_FEATURE_MAX): Define.
(CSKY_CPU_REVERISON_MAX): Define.
(FEATURE_DSP_EXT, FEATURE_DSP, FEATURE_MMU, FEATURE_VDSP,
FEATURE_FLOAT, FEATURE_TRUST, FEATURE_JAVA, FEATURE_SHIELD):
Define, each standard one collection of instructions.
(CSKY_FEATURES_DEF_NULL, CSKY_FEATURES_DEF_e,
CSKY_FEATURES_DEF_t, CSKY_FEATURES_DEF_f, CSKY_FEATURES_DEF_v,
CSKY_FEATURES_DEF_ef, CSKY_FEATURES_DEF_jt,
CSKY_FEATURES_DEF_efht, CSKY_FEATURES_DEF_efv,
CSKY_FEATURES_DEF_eft, CSKY_FEATURES_DEF_d,
CSKY_FEATURES_DEF_df, CSKY_FEATURES_DEF_ft,
CSKY_FEATURES_DEF_tv, CSKY_FEATURES_DEF_fv,
CSKY_FEATURES_DEF_dft, CSKY_FEATURES_DEF_dfv,
CSKY_FEATURES_DEF_ftv, CSKY_FEATURES_DEF_eftv): Define,
the features combination used by cpu.
(CSKY_CPU_REVERISON_r0p0, CSKY_CPU_REVERISON_r1p0,
CSKY_CPU_REVERISON_r2p0, CSKY_CPU_REVERISON_r3p0,
CSKY_CPU_REVERISON_RESERVED, CSKY_CPU_REVERISON_R3):
Define, version information used by cpu.
(csky_cpus): Refine, and add CK804, CK805 and CK800.
(parse_cpu): Refine.
(parse_arch): Refine.
(md_show_usage): Refine.
(md_begin): Refine.
include/
* opcode/csky.h (CSKY_ARCH_804): Define.
(CSKY_ARCH_805): Define.
(CSKY_ARCH_800): Define.
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incldue * opcode/csky.h (CSKY_ISA_FLOAT_7E60): Use a long long type for
this value.
opcodes * csky-dis.c (csky_output_operand): Coerce the immediate values to
long before printing.
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* csky-dis.c (csky_output_operand): Don't sprintf str to itself.
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gas/
* config/tc-csky.c (CSKYV2_ISA_DSP): CSKY_ISA_DSPE60.
(CSKY_ISA_860): Likewise.
include/
* opcode/csky.h (CSKY_ISA_DSPE60): Define.
opcodes/
* csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
ISA flag.
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Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com>
gas/
* config/tc-csky.c (float_work_fpuv3_fmovi): New function,
helper function to encode fpuv3 fmovi instructions.
(float_work_fpuv3_fstore): New function.
(struct literal): Add new member 'offset'.
(csky_cpus): New cpu CK860f.
(enter_literal): Return literal pool pointer instead of offset.
(parse_rt): Adjust the change of enter_literal.
(parse_rtf): Likewise.
(v1_work_lrw): Likewise.
(v1_work_jbsr): Likewise.
(v2_work_lrw): Likewise.
(v2_work_jbsr): Likewise.
(v2_work_jsri): Likewise.
(vdsp_work_vlrw): Likewise.
(is_freglist_legal): Add handler for FPUV3.
(parse_type_freg): Likewise.
(is_imm_within_range): Set e.X_add_number if it is a signed and
negtive number.
(get_operand_value): Add handler for OPRND_TYPE_IMM9b,
OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI
and OPRND_TYPE_DFLOAT_FMOVI.
(float_to_half): Convert float number to harf float.
opcodes/
* csky-dis.c (csky_output_operand): Add handlers for
OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
to support FPUV3 instructions.
* csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
OPRND_TYPE_DFLOAT_FMOVI.
(OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
(csky_v2_opcodes): Add FPUV3 instructions.
include/
* opcode/csky.h (CSKY_ISA_FLOAT_7E60): Define.
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This patch adds support for the system registers introduced in Armv8-R
AArch64.
gas/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* config/tc-aarch64.c (parse_sys_reg): Also pass sysreg name to
validation function.
(parse_sys_ins_reg): Likewise.
(print_operands): Pass CPU features to aarch64_print_operand().
* testsuite/gas/aarch64/v8-r-bad-sysregs.d: New test.
* testsuite/gas/aarch64/v8-r-bad-sysregs.l: Error output.
* testsuite/gas/aarch64/v8-r-bad-sysregs.s: Input.
* testsuite/gas/aarch64/v8-r-sysregs-need-arch.d: New test.
* testsuite/gas/aarch64/v8-r-sysregs-need-arch.l: Error output.
* testsuite/gas/aarch64/v8-r-sysregs.d: New test.
* testsuite/gas/aarch64/v8-r-sysregs.s: Input for previous two tests.
include/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* opcode/aarch64.h (aarch64_sys_ins_reg_supported_p): Also take
system register name in order to simplify validation for v8-R.
(aarch64_print_operand): Also take CPU feature set, as disassembly for
system registers now depends on arch variant.
opcodes/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* aarch64-dis.c (print_operands): Pass CPU features to
aarch64_print_operand().
* aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
preferred disassembly of system registers.
(SR_RNG): Refactor to use new SR_FEAT2 macro.
(SR_FEAT2): New.
(SR_V8_1_A): New.
(SR_V8_4_A): New.
(SR_V8_A): New.
(SR_V8_R): New.
(SR_EXPAND_ELx): New.
(SR_EXPAND_EL12): New.
(aarch64_sys_regs): Specify which registers are only on
A-profile, add R-profile system registers.
(ENC_BARLAR): New.
(PRBARn_ELx): New.
(PRLARn_ELx): New.
(aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
Armv8-R AArch64.
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This adds support for the DFB alias introduced in Armv8-R AArch64.
gas/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* testsuite/gas/aarch64/dfb.d: New test.
* testsuite/gas/aarch64/dfb.s: Input.
opcodes/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* aarch64-tbl.h (aarch64_feature_v8_r): New.
(ARMV8_R): New.
(V8_R_INSN): New.
(aarch64_opcode_table): Add dfb.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
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This patch adds the basic infrastructure needed to support Armv8-R in
AArch64 binutils: new command-line flags, new feature bits, a new BFD
architecture, and support for differentiating between architecture
variants in the disassembler.
The new command-line options added by this patch are -march=armv8-r in
GAS and -m aarch64:armv8-r in objdump.
The disassembler support is necessary since Armv8-R AArch64 introduces a
system register (VSCTLR_EL2) which shares an encoding with a different
system register (TTBR0_EL2) in Armv8-A. This also allows us to use the
correct preferred disassembly for the new DFB alias introduced in
Armv8-R.
bfd/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* archures.c (bfd_mach_aarch64_8R): New.
* bfd-in2.h: Regenerate.
* cpu-aarch64.c (bfd_aarch64_arch_v8_r): New.
(bfd_aarch64_arch_ilp32): Update tail pointer.
gas/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* config/tc-aarch64.c (aarch64_archs): Add armv8-r.
* doc/c-aarch64.texi: Document -march=armv8-r.
include/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_V8_A): New.
(AARCH64_FEATURE_V8_R): New.
(AARCH64_ARCH_V8): Include new A-profile feature bit.
(AARCH64_ARCH_V8_R): New.
opcodes/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* aarch64-dis.c (arch_variant): New.
(determine_disassembling_preference): Disassemble according to
arch variant.
(select_aarch64_variant): New.
(print_insn_aarch64): Set feature set.
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include/
* opcode/v850.h (struct v850_operand <insert>): Make param op an
unsigned long.
opcodes/
* v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
(insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
(insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
(insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
(insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
(insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
(nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
for value parameter and update code to suit.
(extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
(extract_d22, extract_d23, extract_i9): Use unsigned long variables.
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i386-dis.c:12207 left shift of 128 by 24 places cannot be represented in type 'long int'
i386-dis.c:12220 left shift of 128 by 24 places cannot be represented in type 'long int'
i386-dis.c:12222 left shift of 1 by 31 places cannot be represented in type 'long int'
i386-dis.c:12222 signed integer overflow: 162254319 - -2147483648 cannot be represented in type 'long int'
* i386-dis.c (OP_E_memory): Don't cast to signed type when
negating.
(get32, get32s): Use unsigned types in shift expressions.
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* csky-dis.c (print_insn_csky): Use unsigned type for "given".
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* crx-dis.c: Whitespace.
(print_arg): Use unsigned type for longdisp and mask variables,
and for left shift constant.
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bfin-dis.c:160 shift exponent 32 is too large for 32-bit type 'long unsigned int'
bpf-ibld.c:196 left shift of 1 by 31 places cannot be represented in type 'long int'
bpf-ibld.c:196 negation of -2147483648 cannot be represented in type 'long int'; cast to an unsigned type to negate this
itself
bpf-ibld.c:197 left shift of 1 by 31 places cannot be represented in type 'long int'
bpf-ibld.c:197 signed integer overflow: -2147483648 - 1 cannot be represented in type 'long int'
bpf-ibld.c:501 left shift of 1 by 31 places cannot be represented in type 'long int'
* cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
* bpf-ibld.c: Regenerate.
* epiphany-ibld.c: Regenerate.
* fr30-ibld.c: Regenerate.
* frv-ibld.c: Regenerate.
* ip2k-ibld.c: Regenerate.
* iq2000-ibld.c: Regenerate.
* lm32-ibld.c: Regenerate.
* m32c-ibld.c: Regenerate.
* m32r-ibld.c: Regenerate.
* mep-ibld.c: Regenerate.
* mt-ibld.c: Regenerate.
* or1k-ibld.c: Regenerate.
* xc16x-ibld.c: Regenerate.
* xstormy16-ibld.c: Regenerate.
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* bfin-dis.c (MASKBITS): Use SIGNBIT.
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Move divul and divsl to CSKYV2_ISA_3E3R3 instruction set, which is
enabled by ck803r3, and it's still a part of enhance DSP instruction
set.
gas/
* config/tc-csky.c (csky_cpus): Add ck803r3.
(CSKY_ISA_803R3): Define.
(CSKY_ISA_803R2): Refine, use CSKY_ISA_803R1.
include/
* opcode/csky.h (CSKYV2_ISA_3E3R3): Define.
opcodes/
* csky-opc.h (csky_v2_opcodes): Move divul and divsl
to CSKYV2_ISA_3E3R3 instruction set.
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gas/
* testsuite/gas/csky/cskyv2_dsp.d : Fix Encode of mulsws.
opcodes/
* csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
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cpu/
* mep-core.cpu (f-8s8a2, f-12s4a2, f-17s16a2): Multiply signed
value by two rather than shifting left.
(f-24s5a2n): Similarly multiply signed f-24s5a2n-hi to extract.
opcodes/
* mep-ibld.c: Regenerate.
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Rename SET_ERROR_NUMBER to SET_ERROR_STRING, and add SET_ERROR_INTEGER
to report error message which pass an integer argument.
gas/
* config/tc-csky.c (csky_error_state): New member 'arg_int'.
(SET_ERROR_NUMBER): Rename to SET_ERROR_STRING.
(SET_ERROR_INTEGER): New.
(err_formats): Add error format for ERROR_FREG_OVER_RANGE and
ERROR_VREG_OVER_RANGE.
(csky_show_error): Pass an integer argument for some error
numbers.
(parse_exp): Call SET_ERROR_STRING instead of SET_ERROR_NUMBER.
(parse_rt): Likewise.
(parse_type_ctrlreg): Likewise.
(csky_get_reg_val): Likewise.
(is_reglist_legal): Likewise.
(is_freglist_legal): Likewise.
(is_reglist_dash_comma_legal): Likewise.
(is_reg_lshift_illegal): Likewise.
(is_psr_bit): Likewise.
(parse_type_cpreg): Likewise.
(parse_type_cpcreg): Likewise.
(parse_type_areg): Likewise.
(parse_type_freg): Likewise.
(parse_ldst_imm): Likewise and call SET_ERROR_INTEGER.
(get_operand_value): Likewise.
(parse_operands_op): Likewise and call is_imm_within_range,
is_imm_within_range_ext and is_oimm_within_range.
(md_assemble): Likewise.
(is_imm_within_range): New.
(is_imm_within_range_ext): Rename from is_imm_over_range.
(is_oimm_within_range): Rename from is_oimm_over_range.
(v2_work_add_sub): Call SET_ERROR_INTEGER.
(csky_rolc): call is_imm_within_range instead of
is_imm_over_range.
opcodes/
* csky-dis.c (csky_output_operand): Assign dis_info.value for
OPRND_TYPE_VREG.
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When looking at the UB errors, I noticed that cbitb_test.d disassembly
wasn't reproducing the input assembly. That turned out to be an error
in make_argument case arg_cr. This fixes that and makes some general
tidies.
opcodes/
* cr16-dis.c: Formatting.
(parameter): Delete struct typedef. Use dwordU instead
throughout file.
(make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
and tbitb.
(make_argument <arg_cr>): Extract 20-bit field not 16-bit.
gas/
* testsuite/gas/cr16/cbitb_test.d: Update expected output.
* testsuite/gas/cr16/cbitw_test.d: Likewise.
* testsuite/gas/cr16/sbitb_test.d: Likewise.
* testsuite/gas/cr16/sbitw_test.d: Likewise.
* testsuite/gas/cr16/storb_test.d: Likewise.
* testsuite/gas/cr16/storw_test.d: Likewise.
* testsuite/gas/cr16/tbitb_test.d: Likewise.
* testsuite/gas/cr16/tbitw_test.d: Likewise.
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PR 26446
* csky-opc.h (MAX_OPRND_NUM): Define to 5.
(union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
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Eh well, I guess the code didn't quite live up to the comment.
PR 26449
PR 26450
* cgen-ibld.in (insert_1): Use 1UL in forming mask.
(extract_normal): Likewise.
(insert_normal): Likewise, and move past zero length test.
(put_insn_int_value): Handle mask for zero length, use 1UL.
* bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
* ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
* m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
* xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
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bfd
* elf32-csky.c (csky_archs): Fix arch names.
(csky_find_arch_with_name): New.
(elf32_csky_merge_attributes): New.
(csky_elf_merge_private_bfd_data): Add process of merge
attribute section.
(elf32_csky_obj_attrs_arg_type): New.
(elf32_csky_obj_attrs_handle_unknown): New.
(elf_backend_obj_attrs_vendor): Define.
(elf_backend_obj_attrs_section): Define.
(elf_backend_obj_attrs_arg_type): Define.
(elf_backend_obj_attrs_section_type): Define.
binutils/
* readelf.c (get_csky_section_type_name): New.
(get_section_type_name): Add handler for CSKY.
(display_csky_attribute): New.
(process_arch_specific): Add handler for CSKY.
* testsuite/binutils-all/strip-3.d: Remove .csky.attributes
section.
elfcpp/
* elfcpp.h (enum SHT): New enum SHT_CSKY_ATTRIBUTES.
gas/
* gas/config/tc-csky.c (md_begin): Set attributes.
(isa_flag): Change type to unsigned 64 bits.
(struct csky_cpu_info): Likewise.
(struct csky_macro_info): Likewise.
(set_csky_attribute): New.
* testsuite/gas/csky/802j.d: Ignore .csky.attributes section.
* testsuite/gas/csky/all.d: Likewise.
* testsuite/gas/csky/bsr1.d: Likewise.
* testsuite/gas/csky/csky_vdsp.d: Likewise.
* testsuite/gas/csky/cskyv2_all.d: Likewise.
* testsuite/gas/csky/cskyv2_ck803r2.d: Likewise.
* testsuite/gas/csky/cskyv2_ck860.d: Likewise.
* testsuite/gas/csky/cskyv2_dsp.d: Likewise.
* testsuite/gas/csky/cskyv2_elrw.d: Likewise.
* testsuite/gas/csky/cskyv2_float.d: Likewise.
* testsuite/gas/csky/enhance_dsp.d: Likewise.
* testsuite/gas/csky/java.d: Likewise.
* testsuite/gas/csky/v1_float.d: Likewise.
* testsuite/gas/csky/v2_float_part1.d: Likewise.
* testsuite/gas/csky/v2_float_part2.d: Likewise.
* testsuite/gas/csky/v2_tls_gd.d: Likewise.
* testsuite/gas/csky/v2_tls_ie.d: Likewise.
* testsuite/gas/csky/v2_tls_ld.d: Likewise.
* testsuite/gas/csky/v2_tls_le.d: Likewise.
* testsuite/gas/elf/elf.exp: Add handler for CSKY.
* testsuite/gas/elf/section2.e-csky: New.
include/
* elf/csky.h (SHT_CSKY_ATTRIBUTES): Define.
(Tag_CSKY_ARCH_NAME): New enum constant.
(Tag_CSKY_CPU_NAME): Likewise.
(Tag_CSKY_ISA_FLAGS): Likewise.
(Tag_CSKY_DSP_VERSION): Likewise.
(Tag_CSKY_VDSP_VERSION): Likewise.
(Tag_CSKY_FPU_VERSION): Likewise.
(Tag_CSKY_FPU_ABI): Likewise.
(Tag_CSKY_FPU_ROUNDING): Likewise.
(Tag_CSKY_FPU_DENORMAL): Likewise.
(Tag_CSKY_FPU_Exception): Likewise.
(Tag_CSKY_FPU_NUMBER_MODULE): Likewise.
(Tag_CSKY_FPU_HARDFP): Likewise.
(Tag_CSKY_MAX): Likewise.
(VAL_CSKY_DSP_VERSION_EXTENSION): Likewise.
(VAL_CSKY_DSP_VERSION_2): Likewise.
(VAL_CSKY_VDSP_VERSION_1): Likewise.
(VAL_CSKY_VDSP_VERSION_2): Likewise.
(VAL_CSKY_FPU_ABI_SOFT): Likewise.
(VAL_CSKY_FPU_ABI_SOFTFP): Likewise.
(VAL_CSKY_FPU_ABI_HARD): Likewise.
(VAL_CSKY_FPU_HARDFP_HALF): Likewise.
(VAL_CSKY_FPU_HARDFP_SINGLE): Likewise.
(VAL_CSKY_FPU_HARDFP_DOUBLE): Likewise.
* opcode/csky.h (CSKY_ISA_VDSP_V2): Define.
CSKYV1_ISA_E1: Change to long constant type.
CSKYV2_ISA_E1: Likewise.
CSKYV2_ISA_1E2: Likewise.
CSKYV2_ISA_2E3: Likewise.
CSKYV2_ISA_3E7: Likewise.
CSKYV2_ISA_7E10: Likewise.
CSKYV2_ISA_3E3R1: Likewise.
CSKYV2_ISA_3E3R2: Likewise.
CSKYV2_ISA_10E60: Likewise.
CSKY_ISA_TRUST: Likewise.
CSKY_ISA_CACHE: Likewise.
CSKY_ISA_NVIC: Likewise.
CSKY_ISA_CP: Likewise.
CSKY_ISA_MP: Likewise.
CSKY_ISA_MP_1E2: Likewise.
CSKY_ISA_JAVA: Likewise.
CSKY_ISA_MAC: Likewise.
CSKY_ISA_MAC_DSP: Likewise.
CSKY_ISA_DSP: Likewise.
CSKY_ISA_DSP_1E2: Likewise.
CSKY_ISA_DSP_ENHANCE: Likewise.
CSKY_ISA_FLOAT_E1: Likewise.
CSKY_ISA_FLOAT_1E2: Likewise.
CSKY_ISA_FLOAT_1E3: Likewise.
CSKY_ISA_FLOAT_3E4: Likewise.
CSKY_ISA_VDSP: Likewise.
ld/
* emulparams/cskyelf.sh: Support attribute section.
* testsuite/ld-csky/tls-le-v1.d: Match .csky.attributes section.
* ld/testsuite/ld-csky/tls-le.d: Likewise.
* testsuite/ld-elf/non-contiguous.ld: Ignore .csky.attributes
section.
opcodes/
* csky-dis.c (CSKY_DEFAULT_ISA): Define.
(csky_dis_info): Add member isa.
(csky_find_inst_info): Skip instructions that do not belong to
current CPU.
(csky_get_disassembler): Get infomation from attribute section.
(print_insn_csky): Set defualt ISA flag.
* csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
* csky-opc.h (struct csky_opcode): Change isa_flag16 and
isa_flag32'type to unsigned 64 bits.
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opcodes/
* disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
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This patch adds support for xBPF, another ISA targetting the BPF
virtual architecture. For now, the primary difference between eBPF
and xBPF is that xBPF supports indirect calls through the
'call %reg' form of the call instruction.
bfd/
* archures.c (bfd_mach_xbpf): Define.
* bfd-in2.h: Regenerate.
* cpu-bpf.c (bfd_xbpf_arch) New.
(bfd_bpf_arch) Update next in list field to point to xbpf arch.
cpu/
* bpf.cpu (arch bpf): Add xbpf mach and isas.
(define-xbpf-isa) New pmacro.
(all-isas) Add xbpfle,xbpfbe.
(endian-isas): New pmacro.
(mach xbpf): New.
(model xbpf-def): Likewise.
(h-gpr): Add xbpf mach.
(f-dstle, f-srcle, dstle, srcle): Add xbpfle isa.
(f-dstbe, f-srcbe, dstbe, srcbe): Add xbpfbe isa.
(define-alu-insn-un): Use new endian-isas pmacro.
(define-alu-insn-bin, define-alu-insn-mov): Likewise.
(define-endian-insn, define-lddw): Likewise.
(dlind, dxli, dxsi, dsti): Likewise.
(define-cond-jump-insn, define-call-insn): Likewise.
(define-atomic-insns): Likewise.
gas/
* config/tc-bpf.c: Add option -mxbpf to select xbpf isa.
* testsuite/gas/bpf/indcall-1.d: New file.
* testsuite/gas/bpf/indcall-1.s: Likewise.
* testsuite/gas/bpf/indcall-bad-1.l: Likewise.
* testsuite/gas/bpf/indcall-bad-1.s: Likewise.
* testsuite/gas/bpf/bpf.exp: Run new tests.
opcodes/
* bpf-desc.c: Regenerate.
* bpf-desc.h: Likewise.
* bpf-opc.c: Likewise.
* bpf-opc.h: Likewise.
* disassemble.c (disassemble_init_for_target): Set bits for xBPF
ISA when appropriate.
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PR 26504
* vax-dis.c (parse_disassembler_options): Always add at least one
to entry_addr_total_slots.
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bfd/
* bfd-in2.h (bfd_mach_ck860): New.
* cpu-csky.c (arch_info_struct): Add item for CK860.
gas/
* config/tc-csky.c (csky_archs): Add item for CK860,
change ck810 and ck807's arch_flag.
(csky_cpus): Add item for CK860.
(md_begin): Enable DSP for CK810 and CK807 by default.
(md_apply_fix): Fix CKCORE_TLS_IE32 relocation failure.
* gas/testsuite/gas/csky/cskyv2_all.d: Change 'sync 0'
to 'sync'.
* gas/testsuite/gas/csky/cskyv2_all.s: Likewise.
* gas/testsuite/gas/csky/cskyv2_ck860.d: New.
* gas/testsuite/gas/csky/cskyv2_ck860.s: New.
* gas/testsuite/gas/csky/enhance_dsp.d: Change plsli.u16
to plsli.16.
* gas/testsuite/gas/csky/enhance_dsp.s: Likewise.
include/
* opcode/csky.h (CSKYV2_ISA_10E60): New.
(CSKY_ARCH_860): New.
opcode/
* csky-dis.c (csky_find_inst_info): Skip CK860's instructions
in other CPUs to speed up disassembling.
* csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
Change plsli.u16 to plsli.16, change sync's operand format.
Change-Id: I80ec1a9c0cc600d668082a9b91ae6d45b33ec0fc
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gas/
* config/tc-csky.c (CSKY_ISA_803R2): New.
(csky_archs): Add ck803r2 series.
(md_begin): Fix warning about -medsp.
(csky_get_freg_val): Support lowercase of fpu register name.
* testsuite/gas/csky/cskyv2_ck803r2.s: New file.
* testsuite/gas/csky/cskyv2_ck803r2.d: New file.
include/
* csky.h (CSKYV2_ISA_3E3R2): New.
opcodes/
* csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
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enabled.
bfd * elfnn-aarch64.c (_bfd_aarch64_erratum_835769_scan): Only sort
the data map if there are entries in it.
(_bfd_aarch64_erratum_843419_scan): Likewise.
opcodes * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
symbols.
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gas/
* config/tc-csky.c (csky_insn_info): Add member last_isize.
(md_assemble): Assign value to csky_insn.last_isize.
* testsuite/gas/csky/enhance_dsp.d: Test bloop's two operands form.
* testsuite/gas/csky/enhance_dsp.s: Likewise.
opcodes/
* csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
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These shouldn't be optional. The record form of vector instructions
set CR6, giving an expectation that omitting BF should be the same as
specifying CR6.
opcodes/
* ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
vcmpuq and xvtlsbb.
gas/
* testsuite/gas/ppc/int128.s: Correct vcmpuq.
* testsuite/gas/ppc/int128.d: Update.
* testsuite/gas/ppc/xvtlsbb.d: Update.
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The xvcvbf16sp mnemonic has been renamed to xvcvbf16spn, to be consistent
with the other non-signaling conversion instructions which all end with "n".
opcodes/
* ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
<xvcvbf16spn>: ...to this.
gas/
* testsuite/gas/ppc/vsx4.s: Update test to use new mnemonic.
* testsuite/gas/ppc/vsx4.d: Likewise.
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This patch adds support for the system registers introduced in the
Armv8-A MPAM extension.
See https://developer.arm.com/documentation/ddi0598/latest for the
Arm ARM supplement documenting this extension.
gas/ChangeLog:
* testsuite/gas/aarch64/mpam-bad.d: New test.
* testsuite/gas/aarch64/mpam-bad.l: Error output.
* testsuite/gas/aarch64/mpam-bad.s: Input.
* testsuite/gas/aarch64/mpam.d: New test.
* testsuite/gas/aarch64/mpam.s: Input.
opcodes/ChangeLog:
* aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
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* ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
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registers. Fixed with this patch.
* gas/config/tc-aarch64.c (parse_sys_reg): Call to
aarch64_sys_ins_reg_supported_p instead of aarch64_sys_reg_supported_p.
(parse_sys_ins_reg): Add aarch64_sys_reg_deprecated_p check.
* include/opcode/aarch64.h (aarch64_sys_reg_deprecated_p): Functions
paramaters changed.
(aarch64_sys_reg_supported_p): Function removed.
(aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
* opcodes/aarch64-opc.c (aarch64_print_operand):
(aarch64_sys_reg_deprecated_p): Functions paramaters changed.
(aarch64_sys_reg_supported_p): Function removed.
(aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
(aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
into this function.
* gas/testsuite/gas/aarch64/illegal-sysreg-5.d: New test.
* gas/testsuite/gas/aarch64/illegal-sysreg-5.l: New test.
* gas/testsuite/gas/aarch64/sysreg-5.s: New test.
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* ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
instructions.
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gas/
* testsuite/gas/ppc/power8.d,
* testsuite/gas/ppc/power8.s: Add miso.
* testsuite/gas/ppc/power9.d,
* testsuite/gas/ppc/power8.s: Add exser, msgsndu, msgclru.
opcodes/
* ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
Enable icbt for power5, miso for power8.
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gas/
* testsuite/gas/ppc/power8.d: Update.
* testsuite/gas/ppc/vsx2.d: Update.
opcodes/
* ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
mtvsrd, and similarly for mfvsrd.
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Problem found by Tadashi G. Takaoka.
2020-08-04 Christian Groessler <chris@groessler.org>
Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
* z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
opcodes (special "out" to absolute address).
* z8k-opc.h: Regenerate.
2020-08-04 Christian Groessler <chris@groessler.org>
* gas/testsuite/gas/z8k/inout.d: Adapt to correct encoding of
"sout/soutb #imm,reg"
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Use Prefix_XXX for pseudo prefixes. Add {disp16} pseudo prefix and
replace {disp32} pseudo prefix with {disp16} in 16-bit mode test.
Check invalid {disp16}/{disp32} pseudo prefixes.
gas/
PR gas/26305
* config/tc-i386.c (_i386_insn::disp_encoding): Add
disp_encoding_16bit.
(parse_insn): Check Prefix_XXX for pseudo prefixes. Handle
{disp16}.
(build_modrm_byte): Handle {disp16}.
(i386_index_check): Check invalid {disp16} and {disp32} pseudo
prefixes.
* doc/c-i386.texi: Update {disp32} documentation and document
{disp16}.
* testsuite/gas/i386/i386.exp: Run x86-64-inval-pseudo.
* testsuite/gas/i386/inval-pseudo.s: Add {disp32}/{disp16}
tests.
* testsuite/gas/i386/pseudos.s: Add {disp8}/{disp32} vmovaps
tests with 128-byte displacement. Add {disp16} tests.
* testsuite/gas/i386/x86-64-pseudos.s: Add {disp8}/{disp32}
vmovaps test. Add (%r13)/(%r13d) tests.
* testsuite/gas/i386/x86-64-inval-pseudo.l: New file.
* testsuite/gas/i386/x86-64-inval-pseudo.s: Likewise.
* testsuite/gas/i386/inval-pseudo.l: Updated.
* testsuite/gas/i386/pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
opcodes/
PR gas/26305
* i386-opc.h (Prefix_Disp8): New.
(Prefix_Disp16): Likewise.
(Prefix_Disp32): Likewise.
(Prefix_Load): Likewise.
(Prefix_Store): Likewise.
(Prefix_VEX): Likewise.
(Prefix_VEX3): Likewise.
(Prefix_EVEX): Likewise.
(Prefix_REX): Likewise.
(Prefix_NoOptimize): Likewise.
* i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
* i386-tbl.h: Regenerated.
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In s390-mkopc.c, the function insertExpandedMnemonic() searches for the
first occurrence of '*' or '$' in the given mnemonic, and, if a match is
found, chooses an extension table using a switch() on that character. The
switch statement contains a default case that prints an error message and
does not set the extension table. Although this case cannot occur, some
GCC versions obviously conclude that the extension table might have been
left uninitialized after the switch statement and consequently emit
maybe-uninitialized warnings for the variables 'ext_table' and
'ext_table_length'.
Circumvent the warning by handling the unreachable default case with
abort().
opcodes/
* s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
default case with abort() instead of printing an error message and
continuing, to avoid a maybe-uninitialized warning.
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This reverts commit 04c662e2b66bedd050f97adec19afe0fcfce9ea7.
In my underlying suggestion I neglected the fact that in those
cases (,%eiz,1) is the only visible indication that 32-bit
addressing is in effect.
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Change
67 48 8b 1c 25 ef cd ab 89 mov 0x89abcdef(,%eiz,1),%rbx
to
67 48 8b 1c 25 ef cd ab 89 mov 0x89abcdef,%rbx
in AT&T syntax and
67 48 8b 1c 25 ef cd ab 89 mov rbx,QWORD PTR [eiz*1+0x89abcdef]
to
67 48 8b 1c 25 ef cd ab 89 mov rbx,QWORD PTR ds:0x89abcdef
in Intel syntax.
gas/
PR gas/26237
* testsuite/gas/i386/evex-no-scale-64.d: Updated.
* testsuite/gas/i386/addr32.d: Likewise.
* testsuite/gas/i386/x86-64-addr32-intel.d: Likewise.
* testsuite/gas/i386/x86-64-addr32.d: Likewise.
opcodes/
PR gas/26237
* i386-dis.c (OP_E_memory): Don't display eiz with no scale
without base nor index registers.
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... as far as non-fall-through behavior permits.
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Irrespective of their encoding the resulting output should look the
same. Therefore wire the handling of PUSH/POP with GPR operands
encoded in the main opcode byte to the same logic used for other
operands. This frees up yet another macro character.
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