| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-12-07 | RISC-V: Fix 4-arg add parsing. | Jim Wilson | 2 | -1/+6 |
| 2018-12-06 | sim/opcodes: Allow use of out of tree cgen source directory | Andrew Burgess | 3 | -8/+26 |
| 2018-12-06 | opcodes/riscv: Hide '.L0 ' fake symbols | Andrew Burgess | 3 | -0/+28 |
| 2018-12-03 | RISC-V: Accept version, supervisor ext and more than one NSE for -march. | Jim Wilson | 2 | -1/+6 |
| 2018-12-03 | [aarch64] - Only use MOV for disassembly when shifter op is LSL #0 | Egeyar Bagcioglu | 2 | -1/+8 |
| 2018-11-29 | RISC-V: Add missing c.unimp instruction. | Jim Wilson | 2 | -1/+7 |
| 2018-11-27 | RISC-V: Add .insn CA support. | Jim Wilson | 2 | -2/+12 |
| 2018-11-21 | S12Z opcodes: Fix bug disassembling certain shift instructions. | John Darrington | 2 | -19/+30 |
| 2018-11-13 | opcodes/nfp: Fix disassembly of crc[] with swapped operands. | Francois H. Theron | 2 | -6/+10 |
| 2018-11-12 | [BINUTILS, AARCH64, 8/8] Add data cache instructions for Memory Tagging Exten... | Sudakshina Das | 2 | -0/+48 |
| 2018-11-12 | [BINUTILS, AARCH64, 7/8] Add system registers for Memory Tagging Extension | Sudakshina Das | 2 | -0/+35 |
| 2018-11-12 | [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension | Sudakshina Das | 10 | -1642/+1724 |
| 2018-11-12 | [BINUTILS, AARCH64, 5/8] Add Tag getting instruction in Memory Tagging Extension | Sudakshina Das | 5 | -1607/+1633 |
| 2018-11-12 | [BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten... | Sudakshina Das | 8 | -1841/+2036 |
| 2018-11-12 | [BINUTILS, AARCH64, 3/8] Add Pointer Arithmetic instructions in Memory Taggin... | Sudakshina Das | 5 | -1904/+1942 |
| 2018-11-12 | [BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex... | Sudakshina Das | 9 | -2913/+3010 |
| 2018-11-12 | [BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-A | Sudakshina Das | 2 | -0/+10 |
| 2018-11-06 | [BINUTILS, ARM] Add Armv8.5-A to select_arm_features and update macros. | Sudakshina Das | 2 | -5/+10 |
| 2018-11-06 | PowerPC instruction mask checks | Alan Modra | 2 | -141/+72 |
| 2018-11-06 | x86: correctly handle VPBROADCASTD with EVEX.W set outside of 64-bit mode | Jan Beulich | 2 | -1/+6 |
| 2018-11-06 | x86: correctly handle VMOVD with EVEX.W set outside of 64-bit mode | Jan Beulich | 3 | -14/+8 |
| 2018-11-06 | x86: correctly handle KMOVD with VEX.W set outside of 64-bit mode | Jan Beulich | 2 | -32/+17 |
| 2018-11-06 | x86: adjust {,E}VEX.W handling for PEXTR* / PINSR* | Jan Beulich | 5 | -62/+47 |
| 2018-11-06 | x86: adjust {,E}VEX.W handling outside of 64-bit mode | Jan Beulich | 3 | -32/+39 |
| 2018-11-06 | x86: fix various non-LIG templates | Jan Beulich | 3 | -86/+106 |
| 2018-11-06 | x86: allow {store} to select alternative {,}PEXTRW encoding | Jan Beulich | 3 | -11/+16 |
| 2018-11-06 | x86: add more VexWIG | Jan Beulich | 3 | -285/+293 |
| 2018-11-06 | x86: XOP VPHADD* / VPHSUB* are VEX.W0 | Jan Beulich | 3 | -32/+40 |
| 2018-10-23 | S/390: Support vector alignment hints | Andreas Krebbel | 1 | -0/+7 |
| 2018-10-22 | S12Z: Disassembly: Fallback to show the address if the symbol table is empty. | John Darrington | 2 | -0/+9 |
| 2018-10-19 | Arm: Fix disassembler crashing on -b binary when thumb file and thumb not for... | Tamar Christina | 2 | -3/+14 |
| 2018-10-16 | AArch64: Fix error checking for SIMD udot (by element) | Matthew Malcomson | 2 | -1/+7 |
| 2018-10-10 | x86: fold Size{16,32,64} template attributes | Jan Beulich | 5 | -15577/+11696 |
| 2018-10-09 | [PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS | Sudakshina Das | 2 | -0/+23 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers | Sudakshina Das | 2 | -0/+26 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction | Sudakshina Das | 8 | -1136/+1182 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructions | Sudakshina Das | 2 | -0/+16 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction | Sudakshina Das | 2 | -0/+11 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions | Sudakshina Das | 7 | -1089/+1147 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-A | Sudakshina Das | 5 | -1014/+1030 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-A | Sudakshina Das | 5 | -2644/+2766 |
| 2018-10-09 | [PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea... | Sudakshina Das | 2 | -0/+11 |
| 2018-10-08 | AArch64: Replace C initializers with memset | Tamar Christina | 2 | -1/+7 |
| 2018-10-05 | x86: Add Intel ENCLV to assembler and disassembler | H.J. Lu | 4 | -1/+22 |
| 2018-10-05 | [Arm, 2/3] Add instruction SB for AArch32 | Sudakshina Das | 2 | -0/+11 |
| 2018-10-05 | or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns | Richard Henderson | 6 | -29/+163 |
| 2018-10-05 | or1k: Add the l.adrp insn and supporting relocations | Stafford Horne | 9 | -137/+320 |
| 2018-10-05 | or1k: Add relocations for high-signed and low-stores | Richard Henderson | 2 | -272/+172 |
| 2018-10-03 | AArch64: Constraint disassembler and assembler changes. | Tamar Christina | 4 | -11/+104 |
| 2018-10-03 | AArch64: Add SVE constraints verifier. | Tamar Christina | 3 | -1/+358 |
