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2018-10-09[PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-ASudakshina Das1-0/+9
2018-10-09[PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-ASudakshina Das1-0/+11
2018-10-09[PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea...Sudakshina Das1-0/+5
2018-10-08AArch64: Replace C initializers with memsetTamar Christina1-0/+4
2018-10-05x86: Add Intel ENCLV to assembler and disassemblerH.J. Lu1-0/+6
2018-10-05[Arm, 2/3] Add instruction SB for AArch32Sudakshina Das1-0/+5
2018-10-05or1k: Add the l.muld, l.muldu, l.macu, l.msbu insnsRichard Henderson1-0/+9
2018-10-05or1k: Add the l.adrp insn and supporting relocationsStafford Horne1-0/+11
2018-10-05or1k: Add relocations for high-signed and low-storesRichard Henderson1-0/+4
2018-10-03AArch64: Constraint disassembler and assembler changes.Tamar Christina1-0/+9
2018-10-03AArch64: Add SVE constraints verifier.Tamar Christina1-0/+6
2018-10-03AArch64: Refactor verifiers to make more general.Tamar Christina1-0/+5
2018-10-03AArch64: Refactor err_type.Tamar Christina1-0/+5
2018-10-03AArch64: Wire through instr_sequenceTamar Christina1-0/+5
2018-10-03AArch64: Mark sve instructions that require MOVPRFX constraintsTamar Christina1-0/+20
2018-10-02RISC-V: Add fence.tso instructionPalmer Dabbelt1-0/+4
2018-09-23Fix incorrect extraction of signed constants in nios2 disassembler.Sandra Loosemore1-0/+6
2018-09-21csky-opc.h: Initialize fields of last array elementsSimon Marchi1-0/+10
2018-09-20ARC: Fix build errors with large constants and C89Maciej W. Rozycki1-0/+4
2018-09-20Andes Technology has good news for you, we plan to update the nds32 port of b...Nick Clifton1-0/+40
2018-09-17RISC-V: bge[u] should get higher priority than ble[u].Jim Wilson1-0/+4
2018-09-17x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu1-0/+20
2018-09-17x86: Set Vex=1 on VEX.128 only vmovd and vmovqH.J. Lu1-0/+8
2018-09-17x86: Update disassembler for VexWIGH.J. Lu1-0/+387
2018-09-17x86: Replace VexW=3 with VexWIGH.J. Lu1-0/+5
2018-09-15x86: Set VexW=3 on AVX vrsqrtssH.J. Lu1-0/+5
2018-09-15x86: Set Vex=1 on VEX.128 only vmovqH.J. Lu1-0/+8
2018-09-14x86: Support VEX/EVEX WIG encodingH.J. Lu1-0/+7
2018-09-14x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit modeH.J. Lu1-0/+9
2018-09-14x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit modeH.J. Lu1-0/+11
2018-09-14i386: Reformat OP_E_memoryH.J. Lu1-0/+4
2018-09-14x86: fold CRC32 templatesJan Beulich1-0/+5
2018-09-13i386: Update VexW field for VEX instructionsH.J. Lu1-0/+8
2018-09-13x86: drop bogus IgnoreSize from a few further insnsJan Beulich1-0/+9
2018-09-13x86: drop bogus IgnoreSize from AVX512_4* insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from AVX512DQ insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from AVX512BW insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from AVX512VL insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from AVX512ER insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from AVX512F insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from SHA insnsJan Beulich1-0/+5
2018-09-13x86: drop bogus IgnoreSize from XOP and SSE4a insnsJan Beulich1-0/+5
2018-09-13x86: drop bogus IgnoreSize from AVX2 insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from AVX insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from GNFI insnsJan Beulich1-0/+5
2018-09-13x86: drop bogus IgnoreSize from PCLMUL/VPCLMUL insnsJan Beulich1-0/+5
2018-09-13x86: drop bogus IgnoreSize from AES/VAES insnsJan Beulich1-0/+5
2018-09-13x86: drop bogus IgnoreSize from SSE4.2 insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from SSE4.1 insnsJan Beulich1-0/+6
2018-09-13x86: drop bogus IgnoreSize from SSSE3 insnsJan Beulich1-0/+6
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